Analysis of HCS in STI-based LDMOS transistors

A numerical investigation of the hot-carrier behavior of a lateral DMOS transistor with shallow trench isolation (STI) is carried out. The measured drain-current degradation induced by hot-carrier stress (HCS) is nicely reproduced by TCAD results revealing that interface traps are mainly formed at the STI corner close to the channel. The effect of typical device design variations on hot-carrier degradation is analyzed.

[1]  Karl Hess,et al.  MOSFET degradation kinetics and its simulation , 2003 .

[2]  A. Gnudi,et al.  Explanation of the Rugged LDMOS Behavior by Means of Numerical Analysis , 2009, IEEE Transactions on Electron Devices.

[3]  A. Gnudi,et al.  Investigation on saturation effects in the rugged LDMOS transistor , 2009, 2009 21st International Symposium on Power Semiconductor Devices & IC's.

[4]  T. Efland,et al.  A Rugged LDMOS for LBC5 Technology , 2005, Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005..

[5]  P. Hower,et al.  Two-Carrier Current Saturation in a Lateral Dmos , 2006, 2006 IEEE International Symposium on Power Semiconductor Devices and IC's.

[6]  C.M. Liu,et al.  On-Resistance Degradation Induced by Hot-Carrier Injection in LDMOS Transistors With STI in the Drift Region , 2008, IEEE Electron Device Letters.

[7]  E. Rosenbaum,et al.  On the mechanism for interface trap generation in MOS transistors due to channel hot carrier stressing , 2000, IEEE Electron Device Letters.

[8]  D. Lachenal,et al.  Hot-carrier reliability of 20V MOS transistors in 0.13 mum CMOS technology , 2005, Microelectron. Reliab..

[9]  Kuo-Ming Wu,et al.  Convergence of Hot-Carrier-Induced Saturation Region Drain Current and On-Resistance Degradation in Drain Extended MOS Transistors , 2009, IEEE Transactions on Electron Devices.