Architectural Exploration of Chip-Scale Photonic Interconnection Network Designs Using Physical-Layer Analysis

Chip-scale photonic interconnection networks have emerged as a promising technology solution that can address many of the scalability challenges facing the communication networks in next-generation high-performance multicore processors. Photonic interconnects can offer significantly higher bandwidth density, lower latencies, and better energy efficiency. Even though photonics exhibits these inherent advantages over electronics, the network designs that can successfully leverage these benefits cannot be straightforwardly extracted from typical electronic network methodologies and must consider the many unique physical-layer constraints of optical technologies. We conduct an architectural exploration of four chip-scale photonic interconnection networks in a novel simulation environment, measuring insertion loss, crosstalk, and power. We also explain and demonstrate the impact of these physical-layer metrics on the scalability, performance, and realizability of each design.

[1]  A. Varga,et al.  Using the OMNeT++ discrete event simulation system in education , 1999 .

[2]  A. Varga,et al.  THE OMNET++ DISCRETE EVENT SIMULATION SYSTEM , 2003 .

[3]  M. Lipson,et al.  Nanotaper for compact mode conversion. , 2003, Optics letters.

[4]  Uri C. Weiser,et al.  Interconnect-power dissipation in a microprocessor , 2004, SLIP '04.

[5]  W. Elsässer,et al.  Intensity noise properties of quantum cascade lasers. , 2005, Optics express.

[6]  R. Baets,et al.  Focused-Ion-Beam Fabrication of Slanted Grating Couplers in Silicon-on-Insulator Waveguides , 2007, IEEE Photonics Technology Letters.

[7]  Alyssa B. Apsel,et al.  On-Chip Optical Technology in Future Bus-Based Multicore Designs , 2007, IEEE Micro.

[8]  P. Dumon,et al.  Low-loss, low-cross-talk crossings for silicon-on-insulator nanophotonic waveguides. , 2007, Optics letters.

[9]  F. Xia,et al.  Ultracompact optical buffers on a silicon chip , 2007 .

[10]  Qianfan Xu,et al.  12.5 Gbit/s carrier-injection-based silicon micro-ring silicon modulators. , 2007, Optics express.

[11]  C.L. Schow,et al.  Ge-on-SOI-Detector/Si-CMOS-Amplifier Receivers for High-Performance Optical-Communication Applications , 2007, Journal of Lightwave Technology.

[12]  M. Watts,et al.  Ultralow power silicon microdisk modulators and switches , 2008, 2008 5th IEEE International Conference on Group IV Photonics.

[13]  Jung Ho Ahn,et al.  Corona: System Implications of Emerging Nanophotonic Technology , 2008, 2008 International Symposium on Computer Architecture.

[14]  Benjamin G. Lee,et al.  All-Optical Comb Switch for Multiwavelength Message Routing in Silicon Photonic Networks , 2008, IEEE Photonics Technology Letters.

[15]  Howard Wang,et al.  Nanophotonic Optical Interconnection Network Architecture for On-Chip and Off-Chip Communications , 2008, OFC/NFOEC 2008 - 2008 Conference on Optical Fiber Communication/National Fiber Optic Engineers Conference.

[16]  Michal Lipson,et al.  Optical 4x4 hitless Silicon router for optical Networks-on-Chip (NoC): erratum , 2008 .

[17]  K. Bergman,et al.  Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications , 2008, LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society.

[18]  Luca P. Carloni,et al.  Photonic Networks-on-Chip for Future Generations of Chip Multiprocessors , 2008, IEEE Transactions on Computers.

[19]  Leonid Oliker,et al.  Analysis of photonic networks for a chip multiprocessor using scientific applications , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.

[20]  M. Lipson,et al.  Deposited silicon high-speed integrated electro-optic modulator. , 2009, Optics express.

[21]  Christopher Batten,et al.  Building Many-Core Processor-to-DRAM Networks with Monolithic CMOS Silicon Photonics , 2009, IEEE Micro.

[22]  M. Uenuma,et al.  Temperature-independent silicon waveguide optical filter. , 2009, Optics letters.

[23]  K. Bergman,et al.  Multi-wavelength message routing in a non-blocking four-port bidirectional switch fabric for silicon photonic networks-on-chip , 2009, 2009 Conference on Optical Fiber Communication - incudes post deadline papers.

[24]  K. Bergman,et al.  High-Speed 2$\, \times \,$2 Switch for Multiwavelength Silicon-Photonic Networks–On-Chip , 2009, Journal of Lightwave Technology.

[25]  Andrew B. Kahng,et al.  ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.