Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor

This paper presents an interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor. Recent mobile devices need to apply private-information secure technology, such as cipher processing, to prevent the leakage of personal information. However, this adds to the product's required-specifications, especially cipher implementation for fast processing, low power consumption, low hardware cost and adaptability. To satisfy these security-related needs, the interleaved-bitslice method for a massive-parallel SIMD matrix is proposed for parallel block cipher processing with five confidentiality modes on mobile machineries. For the AES algorithm, this processor implementation has up to 93% fewer clock cycles per byte than the conventional mobile processor. Additionally, the MX-1 results are almost constant for all confidentiality modes. Consequently, the interleaved-bitslice block cipher processing with five confidentiality modes on the MX-1 is very effective for implementation of parallel block cipher processing for several mobile devices.

[1]  Changjia Chen,et al.  Using Group Interaction of Players to Prevent In-game Cheat in Network Games , 2007, The First International Symposium on Data, Privacy, and E-Commerce (ISDPE 2007).

[2]  Yannis C. Stamatiou,et al.  Enhancing the security of block ciphers with the aid of parallel substitution box construction , 2002, Proceedings 22nd International Conference on Distributed Computing Systems Workshops.

[3]  Mitsuru Matsui,et al.  On the Power of Bitslice Implementation on Intel Core2 Processor , 2007, CHES.

[4]  Eli Biham,et al.  A Fast New DES Implementation in Software , 1997, FSE.

[5]  K. Dosaka,et al.  A 40GOPS 250mW massively parallel processor based on matrix architecture , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[6]  John Viega,et al.  Secure programming cookbook for C and C , 2003 .

[7]  Takeshi Kumaki,et al.  Realization of efficient and low-power parallel face-detection with massive-parallel memory-embedded SIMD matrix , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[8]  Wei Li,et al.  The Research and Implementation of Reconfigurable Processor Architecture for Block Cipher Processing , 2008, 2008 International Conference on Embedded Software and Systems.

[9]  Chi-Jeng Chang,et al.  The FPGA Implementation of 128-bits AES AlgorithmBased on Four 32-bits Parallel Operation , 2007, The First International Symposium on Data, Privacy, and E-Commerce (ISDPE 2007).

[10]  Chester Rebeiro,et al.  Bitslice Implementation of AES , 2006, CANS.

[11]  Seong-Moo Yoo,et al.  AES crypto chip utilizing high-speed parallel pipelined architecture , 2005, 2005 IEEE International Symposium on Circuits and Systems.