Gate dielectric TDDB characterizations of advanced High-k and metal-gate CMOS logic transistor technology

Transition into High-K (HK) dielectric and Metal-Gate (MG) in advanced logic process has enabled continued technology scaling in support of Moore's law [1-2]. With this, CMOS operating fields have been increasing along with gate dielectric TDDB voltage acceleration factors (VAF). VAF is the most critical reliability parameter used to accurately predict the Gate oxide lifetime (TDDB) at use. This paper highlights low voltage (low-V) TDDB data is critical for the accurate assessment of HK+MG VAF and provides further evidences from both transistor- and product-level data based on 32nm technology generations.

[1]  J. Jopling,et al.  Dielectric breakdown in a 45 nm high-k/metal gate process technology , 2008, 2008 IEEE International Reliability Physics Symposium.

[2]  S. De Gendt,et al.  Degradation and breakdown of 0.9 nm EOT SiO/sub 2/ ALD HfO/sub 2/metal gate stacks under positive constant voltage stress , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  R. Chau,et al.  A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging , 2007, 2007 IEEE International Electron Devices Meeting.

[4]  Mark Y. Liu,et al.  Reliability characterization of 32nm high-K and Metal-Gate logic transistor technology , 2010, 2010 IEEE International Reliability Physics Symposium.

[5]  M. Rafik,et al.  Oxide defects generation modeling and impact on BD understanding , 2011, 2011 International Reliability Physics Symposium.

[6]  Hyunjin Kim,et al.  Frequency dependent TDDB behaviors and its reliability qualification in 32nm high-k/metal gate CMOSFETs , 2011, 2011 International Reliability Physics Symposium.

[7]  Mark Y. Liu,et al.  A 32nm logic technology featuring 2nd-generation high-k + metal-gate transistors, enhanced channel strain and 0.171μm2 SRAM cell size in a 291Mb array , 2008, 2008 IEEE International Electron Devices Meeting.

[8]  T. Nigam,et al.  Accurate model for time-dependent dielectric breakdown of high-k metal gate stacks , 2009, 2009 IEEE International Reliability Physics Symposium.

[9]  J. Jopling,et al.  Characterization of SILC and its end-of-life reliability assessment on 45NM high-K and metal-gate technology , 2009, 2009 IEEE International Reliability Physics Symposium.

[10]  T. Nigam,et al.  Impact of charge trapping on the voltage acceleration of TDDB in metal gate/high-k n-channel MOSFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  R. Kwasnick,et al.  Impact of VLSI technology scaling on HTOL , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).