Nearest neighbour interconnect architecture in deep submicron FPGAs

Several commercial FPGA architectures provide fast connections between adjacent logic blocks that decrease the best-case delay between circuit elements with the goal of increasing overall performance. This paper explores the architecture of these Nearest Neighbour (NN) interconnects to determine topologies, quantities and distances that are best for performance and area. We show that certain architectures can achieve a 7.4% performance improvement at the cost of a 6.3% increase in total FPGA area when fully populated. We also show that a 6.4% improvement can be achieved for a more modest cost of 3.8% increase in area.

[1]  Vaughn Betz,et al.  Effect of the prefabricated routing track distribution on FPGA area-efficiency , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Vaughn Betz,et al.  Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density , 1999, FPGA '99.

[3]  Malgorzata Marek-Sadowska,et al.  Timing driven placement , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[4]  C. D. Gelatt,et al.  Optimization by Simulated Annealing , 1983, Science.

[5]  Vaughn Betz,et al.  Timing-driven placement for FPGAs , 2000, FPGA '00.

[6]  David Lewis,et al.  Using Sparse Crossbars within LUT Clusters , 2001 .

[7]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Vaughn Betz,et al.  Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.

[9]  J. P. Gray,et al.  Configurable hardware: a new paradigm for computation , 1989 .

[10]  Steven J. E. Wilton,et al.  A crosstalk-aware timing-driven router for FPGAs , 2001, FPGA '01.

[11]  Carl Ebeling,et al.  Placement and routing tools for the Triptych FPGA , 1995, IEEE Trans. Very Large Scale Integr. Syst..

[12]  Alexander R. Marquardt,et al.  Cluster-Based Architecture, Timing-Driven Packing and Timing-Driven Placement for FPGAs , 1999 .

[13]  J. Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2000, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[14]  Pierre Marchal,et al.  Field-programmable gate arrays , 1999, CACM.

[15]  Jordan S. Swartz.  A High-Speed Timing-Aware Router for FPGAs , 1998 .

[16]  Vaughn Betz,et al.  A fast routability-driven router for FPGAs , 1998, FPGA '98.

[17]  Robert B. Hitchcock,et al.  Timing Analysis of Computer Hardware , 1982, IBM J. Res. Dev..

[18]  Jonathan Rose,et al.  Mixing buffers and pass transistors in FPGA routing architectures , 2001, FPGA '01.

[19]  Jonathan Rose,et al.  CALL FOR ARTICLES IEEE Design & Test of Computers Special Issue on Microprocessors , 1996 .