Conceptual design of an eight megabyte high performance charge-coupled storage device

The design approach suggested to satisfy the conceptual requirements was the use of self-contained, charge-coupled storage chips with on-chip decoding. In this approach, the information on the memory chip is stored in a group of closed-loop shift registers, and random access is provided to any one of the registers by an on-chip dynamic FET decoder. In this way, n-control lines can select one of 2n shift registers.