The technology to realize Vertically Integrated Circuits (VIC) utilizing interchip vias for the electrical interchip connection in a wafer stack was developed To achieve this advanced 3D integration technology the designated top wafers in the wafer stack were thinned down to 10μm and glued onto the planarized bottom wafers. The realization of the interchip via concept providing vias through the thinned top wafer required the development of plasma etching processes with minimized RIE lags for dielectrics, single crystal silicon, and for the interchip glue layer as well as of extremely highly conformal deposition processes for dielectrics for lateral electrical via isolation with a double dielectric spacer technique and for TiN and W to realize the vertical interchip metallization by void free via refill applying a high aspect ratio W plug technique. The developed technology utilizes CMOS compatible processes exclusively and requires no wafer backside processes.