TAMTAMS: A flexible and open tool for UDSM process-to-system design space exploration
暂无分享,去创建一个
[1] Mahmoud Kamarei,et al. Modified analytical model for subthreshold current in short channel MOSFET's , 2007, IEICE Electron. Express.
[2] Gianluca Piccinini,et al. Statistical power supply dynamic noise prediction in hierarchical power grid and package networks , 2008, Integr..
[3] Jamil Kawa,et al. EDA Challenges in Nano-scale Technology , 2006, IEEE Custom Integrated Circuits Conference 2006.
[4] Oh-Kyong Kwon,et al. A new on-chip interconnect crosstalk model and experimental verification for CMOS VLSI circuit design , 2000 .
[5] R. Schaller,et al. Technological innovation in the semiconductor industry: A case study of the International Technology Roadmap for Semiconductors (ITRS) , 2001, PICMET '01. Portland International Conference on Management of Engineering and Technology. Proceedings Vol.1: Book of Summaries (IEEE Cat. No.01CH37199).
[6] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[7] Atsushi Kurokawa,et al. Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[8] M. Shur,et al. Threshold voltage modeling and the subthreshold regime of operation of short-channel MOSFETs , 1993 .
[9] Kurt Keutzer,et al. System-Level Performance Modeling with BACPAC - Berkeley Advanced Chip Performance Calculator , 1999 .
[10] Gijs Bosman,et al. Model and analysis of gate leakage current in ultrathin nitrided oxide MOSFETs , 2002 .
[11] Jiang Hu,et al. ASIC design flow considering lithography-induced effects , 2008, IET Circuits Devices Syst..
[12] Yu Cao,et al. GTX: the MARCO GSRC technology extrapolation system , 2000, Proceedings 37th Design Automation Conference.
[13] Gianluca Piccinini,et al. UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2 , 2012, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[14] N. Sano,et al. Device modeling and simulations toward sub-10 nm semiconductor devices , 2002 .
[15] K. Roy,et al. Analytical Subthreshold Potential Distribution Model for Gate Underlap Double-Gate MOS Transistors , 2007, IEEE Transactions on Electron Devices.