A "Flying-Adder" frequency synthesis architecture of reducing VCO stages

The "Flying-Adder" architecture is a frequency and phase synthesis technique that is based on a voltage-controlled oscillator (VCO) of multiple delay stages. Since the invention of this architecture, various improvements have been made during many implementations of this technique. One of the remaining issues is to reduce the number of delay stages inside the VCO for the benefit of low power consumption and easy design/layout implementation. This paper presents a modified version of the architecture, by utilizing the scalability presented by Xiu and You, 2002, to achieve this goal. The modified architecture can also be used to improve the number of synthesizable frequencies. The tradeoff for this architecture of reduced-delay-stage VCO is the circuit speed