A Dual-Channel 23-Gbps CMOS Transmitter/Receiver Chipset for 40-Gbps RZ-DQPSK and CS-RZ-DQPSK Optical Transmission

This paper describes a dual-channel 23 (20 to 27) Gbps chipset designed in a 40-nm CMOS process for 40 Gbps differential quadrature phase-shift keying (DQPSK) optical transmission. The transmitter has a 2-tap FIR filter and generates two channels of full-rate data. Data outputs exhibit 10 ps rise/fall times, 0.2 psrms RJ, 0.8 pspp DJ, and a ±0.5 UI skew adjustment relative to the full-rate and half-rate clock outputs. The receiver has two 20-27-Gbps input channels, with each channel including a peaking filter, decision threshold adjustment, and 1-tap loop-unrolled DFE. It achieves a 7- mVppd input sensitivity and a 0.7-UIpp high-frequency jitter tolerance. The transmitter and receiver dissipate 0.63 and 1.2 W, respectively.

[1]  Wei Zhang,et al.  A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber , 2010, IEEE Journal of Solid-State Circuits.

[2]  Y. Amamiya,et al.  A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems , 2009, IEEE Journal of Solid-State Circuits.

[3]  Kentaro Nakamura,et al.  Design Optimization of 40 Gb/s RZ-DQPSK Transceiver for High OSNR and PMD Tolerance under Fast Polarization Changes , 2007 .

[4]  Thomas H. Lee.  The Design of CMOS Radio-Frequency Integrated Circuits , 1998 .

[5]  J.H. Winters,et al.  Techniques for High-Speed Implementation of Nonlinear Cancellation , 1991, IEEE J. Sel. Areas Commun..

[6]  R. Pullela,et al.  A fully integrated 40-Gb/s clock and data recovery IC with 1:4 DEMUX in SiGe technology , 2001 .

[7]  V. Condito,et al.  40-43-Gb/s OC-768 16: 1 MUX/CMU chipset with SFI-5 compliance , 2003, IEEE J. Solid State Circuits.

[8]  N. Tzartzanis,et al.  A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS , 2009, IEEE Journal of Solid-State Circuits.

[9]  Yoshiyasu Doi,et al.  A 3 Watt 39.8–44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS , 2010, IEEE Journal of Solid-State Circuits.

[10]  Shinji Nishimura,et al.  10:4 MUX and 4:10 DEMUX gearbox LSI for 100-gigabit Ethernet link , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Tsunoda Yukito,et al.  40GbE Serial and 40G VSR Compact Optical Transceiver , 2011 .

[12]  John T. Stonick,et al.  A digital clock and data recovery architecture for multi-gigabit/s binary links , 2005, Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005..

[13]  Afshin Momtaz,et al.  A 19 mW/lane Serdes transceiver for SFI-5.1 application , 2011, 2011 IEEE Custom Integrated Circuits Conference (CICC).

[14]  Kazuhisa Takagi,et al.  40G RZ-DQPSK transmitter monolithically integrated with tunable DFB laser array and Mach-Zehnder modulators , 2011, 2011 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference.

[15]  Wei Zhang,et al.  11.3 Gbps CMOS SONET Compliant Transceiver for Both RZ and NRZ Applications , 2011, IEEE J. Solid State Circuits.