Compensation of systematic variations through optimal biasing of SRAM wordlines

Increasing process variability is slowing SRAM scaling by reducing both read and write margins. Existing techniques to compensate for systematic variations optimize cell stability with excessive penalty to writeability. To maximize overall yield, a sensor circuit is presented that optimizes the read / write tradeoff in the presence of process, voltage, and temperature variations. Sensors implemented in a low-power 45 nm test chip adjust the wordline voltage to track changes in the optimal value within 30 mV over the entire range of operation.

[1]  E. Seevinck,et al.  Static-noise margin analysis of MOS SRAM cells , 1987 .

[2]  C. Wann,et al.  SRAM cell design for stability methodology , 2005, IEEE VLSI-TSA International Symposium on VLSI Technology, 2005. (VLSI-TSA-Tech)..

[3]  R. Hollingsworth,et al.  A Screening Methodology for VMIN Drift in SRAM Arrays with Application to Sub-65nm Nodes , 2006, 2006 International Electron Devices Meeting.

[4]  K. Ishibashi,et al.  A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[5]  M. Nomura,et al.  Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring Circuit , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.

[6]  A. Carlson.  Mechanism of Increase in SRAM $V_{\min}$ Due to Negative-Bias Temperature Instability , 2007, IEEE Transactions on Device and Materials Reliability.

[7]  Zheng Guo,et al.  Large-scale read/write margin measurement in 45nm CMOS SRAM arrays , 2008, 2008 IEEE Symposium on VLSI Circuits.