UTILE system: a unified environment from simulation to test

The UTILE (unified test integrated language and environment) system, a unified environment from simulation to test for logic circuits, is described. The system is built around a high-level algorithmic language to describe simulation sequences in terms of functional cycles. The environment provided is independent of the simulator used and the test system, and makes it possible to perform simulation and test-related tasks, from circuit validation to test program generation.<<ETX>>