An embedded tester core for mixed-signal System-on-Chip circuits

Title of Thesis: Modeling and Rendering of Mold on Cut Wood Aimee Joshua, Master of Science, 2005 Thesis directed by:Dr. Marc Olano Often in the rendering of materials such as wood, we are satis fied with an image that is too pristine to exist in the real world. In the real world it is rare to find a piece of wood that is unblemished. Wood imperfections commonly include dirt, c acks, fungi, and mold. Of these, mold is responsible for much of the appearance we asso ci te with weathered wood. Wood that has been cut from a tree, treated, processed, and sh ped is known as cut wood. Cut wood varies in form from wood fences to wood guard posts. C ut wood that has been exposed to weather, in particular moisture and warm tempera tur s, is more likely to have mold form on the surface. We present a method for modeling and re ering weathered cut wood by simulating the growth and presence of mold. We model a piece of wood as a texture map that reflects the prope rties of wood. A mold growth sequence is applied to the texture map to create the lo ok of mold on wood. The technique for creating the mold growth is dependent on time a nd builds upon the surface of the wood model. A generalized mold growth model is impleme nted, reflecting the life cycle of mold over time. A subsurface scattering model is inc orporated that is based on the homogeneous nature of the wood model. The mold on cut wood mod el is applied to two types of wood models, a plank of wood and a more complex wood ob ject. Modeling and Rendering of Mold on Cut Wood

[1]  E. A. Rudge.  The decay of wood , 1935 .

[2]  N. Robertson.  The Growth Process in Fungi , 1968 .

[3]  Michel Gien,et al.  A File Transfer Protocol (FTP) , 1978, Comput. Networks.

[4]  John Nagle,et al.  On Packet Switches with Infinite Storage , 1985, IEEE Trans. Commun..

[5]  Charles E. Leiserson,et al.  Fat-trees: Universal networks for hardware-efficient supercomputing , 1985, IEEE Transactions on Computers.

[6]  V. Jacobson,et al.  Congestion avoidance and control , 1988, SIGCOMM '88.

[7]  Mario Blaum,et al.  The Reliability of Single-Error Protected Computer Memories , 1988, IEEE Trans. Computers.

[8]  Katsumi Dosaka,et al.  An optimized design for high-performance megabit DRAMs , 1989 .

[9]  Jack L. Jewell,et al.  Digital optics , 1989, Proc. IEEE.

[10]  William J. Dally,et al.  Performance Analysis of k-Ary n-Cube Interconnection Networks , 1987, IEEE Trans. Computers.

[11]  Hideto Hidaka,et al.  The cache DRAM architecture: a DRAM with an on-chip cache memory , 1990, IEEE Micro.

[12]  Norman P. Jouppi,et al.  Improving direct-mapped cache performance by the addition of a small fully-associative cache and prefetch buffers , 1990, [1990] Proceedings. The 17th Annual International Symposium on Computer Architecture.

[13]  R. Jain.  Congestion control in computer networks: issues and trends , 1990, IEEE Network.

[14]  Carla Schlatter Ellis,et al.  Exploiting operating system support for dynamic page placement on a NUMA shared memory multiprocessor , 1991, PPOPP '91.

[15]  Carla Schlatter Ellis,et al.  Experimental comparison of memory management policies for NUMA multiprocessors , 1991, TOCS.

[16]  Carla Schlatter Ellis,et al.  Page Placement Policies for NUMA Multiprocessors , 1991, J. Parallel Distributed Comput..

[17]  Anant Agarwal,et al.  Limits on Interconnection Network Performance , 1991, IEEE Trans. Parallel Distributed Syst..

[18]  Richard E. Kessler,et al.  Page placement algorithms for large real-indexed caches , 1992, TOCS.

[19]  Steven McCanne,et al.  The BSD Packet Filter: A New Architecture for User-level Packet Capture , 1993, USENIX Winter.

[20]  Pat Hanrahan,et al.  Reflection from layered surfaces due to subsurface scattering , 1993, SIGGRAPH.

[21]  Walter Willinger,et al.  On the self-similar nature of Ethernet traffic , 1993, SIGCOMM '93.

[22]  Vern Paxson,et al.  Empirically derived analytic models of wide-area TCP connections , 1994, TNET.

[23]  V. Paxson,et al.  Wide-area traffic: the failure of Poisson modeling , 1994, SIGCOMM.

[24]  Walter Willinger,et al.  Analysis, modeling and generation of self-similar VBR video traffic , 1994, SIGCOMM.

[25]  Mark D. Hill,et al.  Surpassing the TLB performance of superpages with less operating system support , 1994, ASPLOS VI.

[26]  Amarnath Mukherjee,et al.  On Long-Range Dependence in NSFNET Traffic , 1994 .

[27]  Brian N. Bershad,et al.  Avoiding conflict misses dynamically in large direct-mapped caches , 1994, ASPLOS VI.

[28]  Anoop Gupta,et al.  Scheduling and page migration for multiprocessor compute servers , 1994, ASPLOS VI.

[29]  Brian N. Bershad,et al.  Reducing TLB and memory overhead using online superpage promotion , 1995, Proceedings 22nd Annual International Symposium on Computer Architecture.

[30]  Walter Willinger,et al.  Self-similarity through high-variability: statistical analysis of Ethernet LAN traffic at the source level , 1997, TNET.

[31]  Oliver Rose,et al.  Statistical properties of MPEG video traffic and their impact on traffic modeling in ATM systems , 1995, Proceedings of 20th Conference on Local Computer Networks.

[32]  Anoop Gupta,et al.  Operating system support for improving data locality on CC-NUMA compute servers , 1996, ASPLOS VII.

[33]  C. L. Chen.  Symbol error correcting codes for memory applications , 1996, Proceedings of Annual Symposium on Fault Tolerant Computing.

[34]  Henning Schulzrinne,et al.  RTP: A Transport Protocol for Real-Time Applications , 1996, RFC.

[35]  Gunnar Karlsson,et al.  Asynchronous transfer of video , 1996, IEEE Commun. Mag..

[36]  Don Towsley,et al.  Packet loss correlation in the MBone multicast network , 1996, Proceedings of GLOBECOM'96. 1996 IEEE Global Telecommunications Conference.

[37]  Roy T. Fielding,et al.  Hypertext Transfer Protocol - HTTP/1.1 , 1997, RFC.

[38]  Sally Floyd,et al.  Why we don't know how to simulate the Internet , 1997, WSC '97.

[39]  Timothy J. Dell,et al.  A white paper on the benefits of chipkill-correct ecc for pc server main memory , 1997 .

[40]  Vern Paxson,et al.  Measurements and analysis of end-to-end Internet dynamics , 1997 .

[41]  Richard Crisp,et al.  Direct RAMbus technology: the new main memory standard , 1997, IEEE Micro.

[42]  R. Wilder,et al.  Wide-area Internet traffic patterns and characteristics , 1997, IEEE Netw..

[43]  Vern Paxson,et al.  An architecture for large-scale Internet measurement , 1998, IEEE Commun. Mag..

[44]  Srinivasan Keshav,et al.  Issues and trends in router design , 1998, IEEE Commun. Mag..

[45]  Leigh Stoller,et al.  Increasing TLB reach using superpages backed by shadow memory , 1998, ISCA.

[46]  Andreas Buja,et al.  XGobi: Interactive Dynamic Data Visualization in the X Window System , 1998 .

[47]  Brad Calder,et al.  Reducing cache misses using hardware and software page placement , 1999, ICS '99.

[48]  Erik Brunvand,et al.  Impulse: building a smarter memory controller , 1999, Proceedings Fifth International Symposium on High-Performance Computer Architecture.

[49]  Georg Carle,et al.  Framework model for packet loss metrics based on loss runlengths , 1999, Electronic Imaging.

[50]  Donald F. Towsley,et al.  Measurement and modelling of the temporal dependence in packet loss , 1999, IEEE INFOCOM '99. Conference on Computer Communications. Proceedings. Eighteenth Annual Joint Conference of the IEEE Computer and Communications Societies. The Future is Now (Cat. No.99CH36320).

[51]  Trevor N. Mudge,et al.  A performance comparison of contemporary DRAM architectures , 1999, ISCA.

[52]  Wenyu Jiang,et al.  QoS Measurement of Internet Real-Time Multimedia Services , 1999 .

[53]  Rajeev Balasubramonian,et al.  Handling PCM Resistance Drift with Device , Circuit , Architecture , and System Solutions , .