SURFACE MOUNT ASSEMBLY AND BOARD LEVEL RELIABILITY FOR HIGH DENSITY POP (PACKAGE-ON-PACKAGE) UTILIZING THROUGH MOLD VIA INTERCONNECT TECHNOLOGY

This paper addresses the recent technological advancements made in the areas of 3D packaging, surface mount and package stacking for next generation high density Packageon-Package (PoP) applications. The PoP architecture integrates high performance logic devices in the bottom package and high capacity or combination memory devices in the top package through a flexible 3D packaging platform. PoP has become an effective solution for smartphones, digital cameras and personal media players due to the flexible integration and business model benefits package stacking provides. As these handheld products converge, the increased functionality will require higher signal processing performance with increased data storage capability thereby increasing interconnection and signal integrity challenges. Next generation PoP technologies must handle these challenges with continued miniaturization, supporting higher interconnect density in a thinner structure with improved warpage control. Convergence of functions in handsets is driving requirements for smaller, thinner, higher density PoP stacks that are projected to exceed the capability of current bottom package stackable technologies. The standardization of the memory interface has accelerated PoP adoption, but to support the increased functionality in convergence products, a next generation bottom package technology is required that provides a higher density memory interface that will support low power DDR2 and non volatile memory architectures. The future memory interface must enable higher data transfer rates, wider bus and higher memory capacities - resulting in the need for a finer pitch, higher density interface between the stackable packages. Ideally the next generation bottom package platform will allow the memory interface to scale with fine pitch BGA pitch trends without requiring new SMT processes to be developed. Trends in logic devices are driving integration of multi band modems and application processors that operate at higher clock speeds. This integration can be provided in dual die or dual core solutions. Either solution increases signal processor functionality, pin count and interconnect density creating packaging and signal integrity challenges by themselves but further complicated for PoP applications due to the future memory interface challenges introduced above. Thus, the next generation bottom PoP technology must support, dual die (including stacked die) for wire bond or flip chip devices in addition to passive component integration for improved signal integrity while providing a flat and scaleable high density memory interface. This paper summarizes the new mechanically-balanced bottom package structure that Amkor presented at ECTC this past May. This paper describes how this new package addresses the current and next generation PoP requirements by the use of a solderable through mold electrical interconnect structure. This paper provides data from a warpage control, SMT stacking and board level reliability joint study between Amkor and Sony Ericsson Mobile Communications (SEMC). Board level reliability performance improvement is demonstrated by comparing this new package structure with a conventional exposed thin die flip chip bottom stackable package. A 14 x 14mm (less than 1.4mm thick) PoP test vehicle was developed using a six net daisy chain design to fully evaluate the mechanical reliability of first and second level interconnects. The test vehicle provides two nets for the 620 bottom BGAs at 0.4mm pitch, two nets for the 200 pin top interface at 0.5mm pitch and separate nets for the thin daisy chain FC die. In addition, the test vehicle used 01005 sized zero ohm resistors to represent decoupling caps. This paper also summarizes the PoP size reduction that can be achieved for the benefits of a memory interface technology that can scale to 0.3mm pitch requirements.