Fault detection and diagnosis based on signature analysis

An examination is made of widely accepted assumptions underlying the analysis of aliasing phenomena and related problems when using linear feedback shift registers. An extensive fault simulation has been used as a tool to collect the required data characterizing the behavior of these circuits together with the test response compactors implemented by LFSRs and MISRs. At least five million test vectors have been simulated and more than 15000 faults have been analyzed in order to obtain the realistic values of such quantities as the fault coverage after compaction, the aliasing probability as a function of a number of tests applied or the number of times a fault is detected, and the histograms of aliased faults. It is shown that the theoretical models of compaction procedures using LFSRs or MISRs yield results very close to those obtained from experiments performed in the fault domain.<<ETX>>

[1]  Janusz Rajski,et al.  A method of fault simulation based on stem regions , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Janusz Rajski,et al.  On the diagnostic resolution of signature analysis , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[3]  J. A. Waicukauski.  Diagnosis of BIST Failures by PPSFP simulation , 1987 .

[4]  Michele Favalli,et al.  Aliasing in signature analysis testing with multiple input shift registers , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Michele Favalli,et al.  An analytical model for the aliasing probability in signature analysis testing , 1989, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  André Ivanov,et al.  An iterative technique for calculating aliasing probability of linear feedback signature registers , 1988, [1988] The Eighteenth International Symposium on Fault-Tolerant Computing. Digest of Papers.

[7]  Wilfried Daehn,et al.  Comparison of Aliasing Errors for Primitive and Non-Primitive Polynomials , 1986, ITC.

[8]  Dhiraj K. Pradhan,et al.  Aliasing Probability for Multiple Input Signature Analyzer , 1990, IEEE Trans. Computers.

[9]  Sudhakar M. Reddy,et al.  A Data Compression Technique for Built-In Self-Test , 1988, IEEE Trans. Computers.

[10]  André Ivanov,et al.  Experiments on aliasing in signature analysis registers , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[11]  Edward McCluskey,et al.  Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.

[12]  Vinod K. Agarwal,et al.  A diagnosis method using pseudo-random vectors without intermediate signatures , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[13]  Prawat Nagvajara,et al.  Optimal Robust Compression of Test Responses , 1990, IEEE Trans. Computers.

[14]  Wilfried Daehn,et al.  Bounds and analysis of aliasing errors in linear feedback shift registers , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  James E. Smith,et al.  Measures of the Effectiveness of Fault Signature Analysis , 1980, IEEE Transactions on Computers.

[16]  K. Iwasaki,et al.  An analysis of the aliasing probability of multiple-input signature registers in the case of a 2m-ary symmetric channel , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..