A single event upset tolerant latch with parallel nodes
暂无分享,去创建一个
Xuan Zeng | Qiang Zhao | Xiangdong Hu | Xiulong Wu | Chunyu Peng | Changyong Liu | Zhiting Lin | Junning Chen | Xuan Li | Nianlong Liu | Xuan Zeng | Junning Chen | Xiulong Wu | Chunyu Peng | Nianlong Liu | Zhiting Lin | Qiang Zhao | Changyong Liu | Xuan Li | Xiangdong Hu
[1] Adrian Evans,et al. Detailed SET Measurement and Characterization of a 65 nm Bulk Technology , 2017, IEEE Transactions on Nuclear Science.
[2] Xu Hui,et al. Circuit and layout combination technique to enhance multiple nodes upset tolerance in latches , 2015, IEICE Electron. Express.
[3] Xiaoqing Wen,et al. A Double-Node-Upset Self-Recoverable Latch Design for High Performance and Low Power Application , 2019, IEEE Transactions on Circuits and Systems II: Express Briefs.
[4] Xin Xie,et al. A novel highly reliable and low-power radiation hardened SRAM bit-cell design , 2018, IEICE Electron. Express.
[5] Huaguo Liang,et al. A transient pulse dually filterable and online self-recoverable latch , 2017, IEICE Electron. Express.
[6] Shuming Chen,et al. Simulation Study of the Layout Technique for P-hit Single-Event Transient Mitigation via the Source Isolation , 2012, IEEE Transactions on Device and Materials Reliability.
[7] Xin Xie,et al. A novel SEU tolerant memory cell for space applications , 2018, IEICE Electron. Express.
[8] SheXiao Xuan,et al. SEU Hardened Flip-Flop Based on Dynamic Logic , 2013, IEEE Transactions on Nuclear Science.
[9] Robert Baumann,et al. Soft errors in advanced computer systems , 2005, IEEE Design & Test of Computers.
[10] Maryam Shojaei Baghini,et al. Robust Soft Error Tolerant CMOS Latch Configurations , 2016, IEEE Transactions on Computers.
[11] L. W. Massengill,et al. Effect of Multiple-Transistor Charge Collection on Single-Event Transient Pulse Widths , 2011, IEEE Transactions on Device and Materials Reliability.
[12] Anton O. Balbekov,et al. Circuit-Level Layout-Aware Modeling of Single-Event Effects in 65-nm CMOS ICs , 2018, IEEE Transactions on Nuclear Science.
[13] Ivan R. Linscott,et al. LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.
[14] R. Baumann. Soft errors in advanced semiconductor devices-part I: the three radiation sources , 2001 .
[15] Qiang Zhao,et al. A dual-output hardening design of inverter chain for P-hit single-event transient pulse elimination , 2018, IEICE Electron. Express.
[16] J. Teifel,et al. Self-Voting Dual-Modular-Redundancy Circuits for Single-Event-Transient Mitigation , 2008, IEEE Transactions on Nuclear Science.
[17] Fabrizio Lombardi,et al. Design and Performance Evaluation of Radiation Hardened Latches for Nanoscale CMOS , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[18] Xin Xie,et al. A novel self-recoverable and triple nodes upset resilience DICE latch , 2018, IEICE Electron. Express.
[19] J. S. Kauppila,et al. An Area Efficient Stacked Latch Design Tolerant to SEU in 28 nm FDSOI Technology , 2016, IEEE Transactions on Nuclear Science.
[20] Lloyd W. Massengill,et al. Basic mechanisms and modeling of single-event upset in digital microelectronics , 2003 .
[21] B. L. Bhuva,et al. Double-pulse-single-event transients in combinational logic , 2011, 2011 International Reliability Physics Symposium.
[22] Qiang Zhao,et al. An inverter chain with parallel output nodes for eliminating single-event transient pulse , 2019, IEICE Electron. Express.
[23] B.L. Bhuva,et al. RHBD techniques for mitigating effects of single-event hits using guard-gates , 2005, IEEE Transactions on Nuclear Science.
[24] B L Bhuva,et al. Independent Measurement of SET Pulse Widths From N-Hits and P-Hits in 65-nm CMOS , 2010, IEEE Transactions on Nuclear Science.
[25] P E Dodd,et al. Current and Future Challenges in Radiation Effects on CMOS Electronics , 2010, IEEE Transactions on Nuclear Science.
[26] Shuming Chen,et al. Novel Layout Technique for Single-Event Transient Mitigation Using Dummy Transistor , 2013, IEEE Transactions on Device and Materials Reliability.
[27] Mohammad Eshghi,et al. Design and Evaluation of an Efficient Schmitt Trigger-Based Hardened Latch in CNTFET Technology , 2017, IEEE Transactions on Device and Materials Reliability.
[28] Lloyd W. Massengill,et al. Impact of scaling on soft-error rates in commercial microprocessors , 2002 .
[29] Ziyang Chen,et al. A radiation harden enhanced Quatro (RHEQ) SRAM cell , 2017, IEICE Electron. Express.
[30] P. Marshall,et al. 32 and 45 nm Radiation-Hardened-by-Design (RHBD) SOI Latches , 2011, IEEE Transactions on Nuclear Science.