In this paper, the novel mechanical switch device: suspended-gate FET is applied to FPGA development. This device offers almost an ideal subthreshold swing and a hysteretic resistance switching, opening opportunities for low-power applications. The proposed device can be used as the building block of programmable elements and memory of an FPGA. Based on this device, the proposed FPGA architecture, SG-FPGA, can maintain the baseline FPGA architecture and significantly reduce the size and power consumption of the memory and routing elements. The simulation results demonstrate that the application of SG-FET to FPGA chips can provide at least 3X-5X performance gains in terms of density and power.
[1]
Wei Wang,et al.
rFGA: CMOS-nano hybrid FPGA using RRAM components
,
2008,
2008 IEEE International Symposium on Nanoscale Architectures.
[2]
Guy Lemieux,et al.
Circuit design of routing switches
,
2002,
FPGA '02.
[3]
H.-S.P. Wong,et al.
Analytical Modeling of the Suspended-Gate FET and Design Insights for Low-Power Logic
,
2008,
IEEE Transactions on Electron Devices.
[4]
Wei Wang,et al.
3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits
,
2007,
IEEE Transactions on Circuits and Systems I: Regular Papers.