An optimum ADC output word length selection for low power communication architectures

Low power Very Large Scale Integration (VLSI) design for communication applications is key technology area, driving current mobile communication and wireless networking sectors. The decades of research in Complementary Metal Oxide Semiconductor (CMOS) VLSI technologies could achieve low power design procedures at transistor and circuit level design. To further achieve low power, the researchers are looking at system level design by adopting suitable algorithms and architectures. This paper illustrates one of the power optimization techniques, by reducing the number of ADC output bits, while considering the system level parameters. The dynamic ADC word length optimizer (WLO) is prototyped in VHDL and verified for its functionality in practical signal conditions. The architecture is synthesized for Spartan-6 SX45T FPGA and results demonstrate maximum clock speeds up to 200 MHz, ensuring its compatibility with all types of wideband communication applications with high speed ADCs. Power analysis carried out with Xpower tool show power reduction by 40%. The proposed WLO is simulated and verified for BPSK demodulation, to achieve the theoretical BER limit of 10-5 at 9.5 dB SNR value.