409ps 4.7 FO4 64b adder based on output prediction logic in 0.18um CMOS

We present a fast 64b adder based on output prediction logic (OPL) that has a measured worst-case delay of 409ps, equivalent to 4.7 FO4 inverter delays for the TSMC 0.18/spl mu/m process that was used for fabrication. This normalized delay is 1.45X faster than the fastest previously reported 64b adder. The adder uses a modified radix-3 Kogge-Stone architecture and has 5 logic levels.

[1]  Ching-Te Chuang,et al.  SOI-optimized 64-bit high-speed CMOS adder design , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).

[2]  K. Soumyanath,et al.  Sub-500-ps 64-b ALUs in 0 . 18-m SOI / Bulk CMOS : Design and Scaling Trends , 2001 .

[3]  Huey Ling.  High Speed Binary Adder , 1981, IBM J. Res. Dev..

[4]  Denis Flandre,et al.  Power-delay product minimization in high-performance 64-bit carry-select adders , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  S.H. Dhong,et al.  470 ps 64-bit parallel binary adder [for CPU chip] , 2000, 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103).

[6]  Carl Sechen,et al.  A low power delayed-clocks generation and distribution system , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[7]  Ken Mai,et al.  The future of wires , 2001, Proc. IEEE.

[8]  K. Soumyanath,et al.  Sub-500 ps 64 b ALUs in 0.18 /spl mu/m SOI/bulk CMOS: Design & scaling trends , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[9]  Simon Knowles,et al.  A family of adders , 1999, Proceedings 14th IEEE Symposium on Computer Arithmetic (Cat. No.99CB36336).

[10]  D. L. Stasiak,et al.  A 440-ps 64-bit adder in 1.5-V/0.18-/spl mu/m partially depleted SOI technology , 2001 .

[11]  Carl Sechen,et al.  Application of output prediction logic to differential CMOS , 2001, Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems.

[12]  F. Klass.  Semi-dynamic and dynamic flip-flops with embedded logic , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[13]  Tyler Thorp,et al.  Output prediction logic: a high-performance CMOS design technique , 2000, Proceedings 2000 International Conference on Computer Design.

[14]  Hoi-Jun Yoo,et al.  480 ps 64-bit race logic adder , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).