Semiconductor memory device with improved driver for the sense amplifier

A semiconductor memory device, comprising: a plurality of memory cell arrays (i, j, k, l, m, ...); a sense amplifier array (S / A) corresponding to each memory cell array, where each sense amplifier array having a plurality of sense amplifiers (SA), memory cells associated with a corresponding memory cell array, each sense amplifier of a column and a bit line (BL0) and a complementary bit line includes (BL0B), said bit line and the complementary bit line (BL0, BL0B) are used to load data stored in a memory cell; each sense amplifier arrangement corresponding input / output lines; a plurality of sense amplifier drivers (SYD), each sense amplifier driver (SYD) at least one sense amplifier (SA) is allocated and the bit line and the complementary bit line (BL0, BL0B) of the associated sense amplifier (SA) selectively (with the corresponding input / output lines SAIO, SAIOB) (on the basis of at least one column address selection signal and an inverse of the column address selection signal YSEL, YSELB) and at least one column group selection signal and an inverse of the column group select signal (CBSEL, CBSELB) connects; a column decoder which decodes a column address signal indicating a column address of a selected memory cell to the column address select signal (YSEL) ...