An Efficient BIST Scheme for Two-Pattern Test

This paper presented an more efficient BIST scheme for two-pattern test based on the in-depth research of the advantages and disadvantages of the already presented scheme, the framework of the presented BIST scheme is constituted by the linear feedback shift registers (LFSR) and the corresponding mapping logics. In addition, we put forward a new and efficient arithmetic to compute the best combinations of the seeds and the feedback polynomials of LFSR. In the last part of the paper, we used this presented BIST scheme to implement the Maximal Aggressor Fault model (MAF) for the crosstalk faults on SoC interconnects, which is a typical two-pattern test problem. The results show the superiority of this presented BIST scheme for two-pattern test in the area overhead and the computing complexity.