A Global Replacement Based on Actual Set Association

Recently, to reduce conflict misses introduced by the non-uniform distribution of memory references, global replacement is explored in set-associative cache. We propose a novel low-overhead global replacement mechanism based on actual set association. In our mechanism, the global replacement is partitioned into global set selection and local LRU replacement within set allowing data resources contention among sets. For the twelve benchmarks from SPEC CPU2000 suite, our mechanism can achieve an average miss rate reduction of 20.94% close to global LRU replacement with an extra storage cost of about 4.63%, compared to a baseline set-associative cache.

[1]  Dean M. Tullsen,et al.  Fellowship - Simulation And Modeling Of A Simultaneous Multithreading Processor , 1996, Int. CMG Conference.

[2]  Yannis Smaragdakis,et al.  Adaptive Caches: Effective Shaping of Cache Behavior to Workloads , 2006, 2006 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO'06).

[3]  Steven K. Reinhardt,et al.  A fully associative software-managed cache design , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).

[4]  Brad Calder,et al.  Basic block distribution analysis to find periodic behavior and simulation points in applications , 2001, Proceedings 2001 International Conference on Parallel Architectures and Compilation Techniques.

[5]  André Seznec,et al.  A case for two-way skewed-associative caches , 1993, ISCA '93.

[6]  Yale N. Patt,et al.  The V-Way Cache: Demand Based Associativity via Global Replacement , 2005, ISCA 2005.

[7]  Mateo Valero,et al.  Eliminating cache conflict misses through XOR-based placement functions , 1997, ICS '97.

[8]  Aamer Jaleel,et al.  Adaptive insertion policies for high performance caching , 2007, ISCA '07.

[9]  J. T. Robinson,et al.  Data cache management using frequency-based replacement , 1990, SIGMETRICS '90.

[10]  Onur Mutlu,et al.  A Case for MLP-Aware Cache Replacement , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[11]  Jaejin Lee,et al.  Using prime numbers for cache indexing to eliminate conflict misses , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

[12]  Margaret Martonosi,et al.  Timekeeping in the memory system: predicting and optimizing memory behavior , 2002, ISCA.

[13]  Margaret Martonosi,et al.  Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.