Fault tolerant arithmetic unit using duplication and residue codes

Abstract This paper is a study of the practical value of the various approaches, proposed so far, to achieve fault tolerance in arithmetic units using the residue code technique and to find the best design in terms of cost and error coverage. The results have shown that the error correction approaches can treat a one-bit error (E = ± 2i) using relatively small hardware cost and time delay. It is also shown that no more than a single error, of the one-bit type, can be treated at reasonable cost using error correction approaches. However, a combination of N-modular redundancy (NMR) and residue codes can be used to cover a wide range of errors at considerably lower cost. Here we suggest anapproach based on model duplication and residue codes (DAR) which is shown to have better error coverage than error correction approaches and lower cost than both triple modular redundancy (TMR) and error correction approaches.

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