Rapid technology projection for high-level synthesis

High-level synthesis (HLS) tools often use parameterized RT component generators during component selection and allocation. Rapid and accurate technology-specific estimates are therefore crucial for performing effective design space exploration. We describe a fast (on-line) method for estimating the area and delay of regular-structured generic RT components tuned to a particular technology library. The estimation models are generated using a least-square approximation on a set of sample technology data points from selected component implementations. We tested these models against real data points on combinational and sequential components and observed an average error of within 10%. The estimators are integrated with a HLS system to provide on-line technology projection of RT components.<<ETX>>

[1]  D.D. Gajski,et al.  An algorithm for component selection in performance optimized scheduling , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[2]  Rajiv Jain,et al.  Area-time model for synthesis of non-pipelined designs , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[3]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[4]  Robert K. Brayton,et al.  MIS: A Multiple-Level Logic Optimization System , 1987, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[5]  Fadi J. Kurdahi,et al.  LAST: a layout area and shape function estimator for high level applications , 1991, Proceedings of the European Conference on Design Automation..

[6]  F.J. Kurdahi,et al.  TELE: a timing evaluator using layout estimation for high level applications , 1992, [1992] Proceedings The European Conference on Design Automation.

[7]  Nikil Dutt.  Generic component library characterization for high level synthesis , 1991, [1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design.

[8]  Viraphol Chaiyakul,et al.  Timing models for high-level synthesis , 1992, Proceedings EURO-DAC '92: European Design Automation Conference.

[9]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[10]  Nikil D. Dutt,et al.  Bridging high-level slqvihesis to RTL technology libraries , 1991, 28th ACM/IEEE Design Automation Conference.

[11]  David E. Wallace,et al.  High-level delay estimation for technology-independent logic equations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[12]  Akhilesh Tyagi.  An algebraic model for design space with applications to function module generation , 1990, Proceedings of the European Design Automation Conference, 1990., EDAC..

[13]  Daniel D. Gajski,et al.  Synthesis from VHDL , 1988, Proceedings 1988 IEEE International Conference on Computer Design: VLSI.

[14]  Rajiv Jain.  MOSP: module selection for pipelined designs with multi-cycle operations , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.