Highly reliable solid-state drives (SSDs) with error-prediction LDPC (EP-LDPC) architecture and error-recovery scheme
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[1] Jungdal Choi,et al. Effects of floating-gate interference on NAND flash memory cell operation , 2002 .
[2] Young-Hyun Jun,et al. A 21nm high performance 64Gb MLC NAND flash memory with 400MB/s asynchronous toggle DDR interface , 2011, 2011 Symposium on VLSI Circuits - Digest of Technical Papers.
[3] Shuhei Tanakamaru,et al. 95%-lower-BER 43%-lower-power intelligent solid-state drive (SSD) with asymmetric coding and stripe pattern elimination algorithm , 2011, 2011 IEEE International Solid-State Circuits Conference.
[4] Shuhei Tanakamaru,et al. Over-10×-extended-lifetime 76%-reduced-error solid-state drives (SSDs) with error-prediction LDPC architecture and error-recovery scheme , 2012, 2012 IEEE International Solid-State Circuits Conference.