Power consumption contrasting model for different logarithmic active pixel sensor topologies

The literature presents many different active pixel sensor (APS) topologies operating in the high dynamic range logarithmic mode, as well as, different techniques to improve image quality by attenuating fixed-pattern noise (FPN). Together with the proposed solution, the advantages and disadvantages of each new solution are usually presented in their published reports. However, it is hard to find different solutions developed for the very same CMOS technology, and there is no standard model to effectively contrast their effectiveness according to parameters such as power consumption. This work analyses the power consumption of different logarithmic mode CMOS APSs topologies employing different FPN attenuation techniques. The purpose of such a study is the establishment of a way to contrast different solutions designed in the same CMOS technology, so that one can easily make a decision on what solution to choose based on different parameters, including power consumption.

[1]  Davies W. de Lima Monteiro,et al.  Voltage Mode FPN Calibration in the Logarithmic CMOS Imager , 2015 .

[2]  Qing Gao,et al.  A Low-Power Block-Based CMOS Image Sensor With Dual VDD , 2012, IEEE Sensors Journal.

[3]  C. Cruz.  Simplified wide dynamic range CMOS image sensor with 3t APS reset-drain actuation , 2014 .

[4]  A. El Gamal,et al.  CMOS image sensors , 2005, IEEE Circuits and Devices Magazine.

[5]  L. Greggain,et al.  Predicting and scaling power consumption in CMOS ASICs , 1989, Proceedings., Second Annual IEEE ASIC Seminar and Exhibit,.

[6]  Zhihua Wang,et al.  A low power CMOS image sensor design for wireless endoscopy capsule , 2008, 2008 IEEE Biomedical Circuits and Systems Conference.

[7]  David Harris,et al.  CMOS VLSI Design: A Circuits and Systems Perspective , 2004 .

[8]  Anantha P. Chandrakasan,et al.  Minimizing power consumption in digital CMOS circuits , 1995, Proc. IEEE.

[9]  Renato P. Ribas,et al.  Power consumption analysis in static CMOS gates , 2013, 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI).

[10]  G. Sicard,et al.  An on-pixel FPN reduction method for a high dynamic range CMO S imager , 2007, ESSCIRC 2007 - 33rd European Solid-State Circuits Conference.

[11]  Gilles Sicard,et al.  A high output voltage swing logarithmic image sensor designed with on chip FPN reduction , 2010, 6th Conference on Ph.D. Research in Microelectronics & Electronics.

[12]  Enrico Macii,et al.  Power consumption of static and dynamic CMOS circuits: a comparative study , 1996, 2nd International Conference on ASIC.

[13]  S. Pravossoudovitch,et al.  Technique for reducing power consumption in CMOS circuits , 1997 .