Metrology of most advanced CMOS devices poses more and more challenges: lithography and etch patterning processes need to be controlled on critical parameters that -beyond critical dimensions (CD)- nowadays also include line width and line edge roughness (LWR/LER), multiple patterning induced pitch-walk and, due to the high aspect ratio of the patterned structures, also thermo-mechanical structural bending. In this paper, it is shown that sufficient sampling is required to ensure that scanning transmission electron microscopy (STEM) does provide relevant information about the dimensions and chemical composition of the advanced devices. While, in principle, STEM can measure device dimensions with Angstrom resolution and sub-nm precision, a single measurement will not be representative for the device dimensions that are known to vary statistically (LER/LWR) as well as systematically (Pitch-walk, structural bending). In this context, the metrology capabilities of a (calibrated) automated 80-200kV STEM with Cs aberration corrector and a high efficiency EDS detector have been evaluated for both STEM-EDS and STEM-HAADF acquisitions. It will be shown that, when measuring multiple (~ 400) individual FinFET structures (Silicon Fins / dummy Silicon gate lines), average CD, LER and LWR can be quantified from the distribution of measured line widths and line pitches, that SADP and SAQP induced pitch-walk may show up as multi-modal pitch distributions, and that pitch walking can be quantified if also structural bending, that is observed, is properly taken into account. Finally, the STEM and EDS metrology capabilities for FinFET and NanoWire (NW) device structures are reviewed for different use cases (statistical process control and technology development support) and with different indicators (Precision over Tolerance ratio (P/T) and Variability ratio (r = 1 – σ2 metrology / σ2 measured process )).