GSSA: A Resource Allocation Scheme Customized for 3D NAND SSDs
暂无分享,去创建一个
Mahmut T. Kandemir | Chita R. Das | Myoungsoo Jung | Wonil Choi | Chun-Yi Liu | Yunju Lee | M. Kandemir | C. Das | Myoungsoo Jung | Wonil Choi | Chun-Yi Liu | Yunju Lee
[1] Mohammad Arjomand,et al. Exploring the Potentials of Parallel Garbage Collection in SSDs for Enterprise Storage Systems , 2016, SC16: International Conference for High Performance Computing, Networking, Storage and Analysis.
[2] Steven Swanson,et al. Gordon: using flash memory to build fast, power-efficient clusters for data-intensive applications , 2009, ASPLOS.
[3] Mahmut T. Kandemir,et al. PEN: Design and Evaluation of Partial-Erase for 3D NAND-Based High Density SSDs , 2018, FAST.
[4] Wei-Kuan Shih,et al. Boosting the performance of 3D charge trap NAND flash with asymmetric feature process size characteristic , 2017, 2017 54th ACM/EDAC/IEEE Design Automation Conference (DAC).
[5] Yi Wang,et al. A Thermal-Aware Physical Space Allocation Strategy for 3D Flash Memory Storage Systems , 2016, ISLPED.
[6] Ying Yu,et al. 11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technology , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[7] Xu Li,et al. A 512Gb 3b/Cell 3D flash memory on a 96-word-line-layer technology , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).
[8] Ki-Hong Lee,et al. Inherent Issues and Challenges of Program Disturbance of 3D NAND Flash Cell , 2012, 2012 4th IEEE International Memory Workshop.
[9] Myoungjun Chun,et al. Exploiting Process Similarity of 3D Flash Memory for High Performance SSDs , 2019, MICRO.
[10] Yan Li,et al. A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology , 2009, IEEE Journal of Solid-State Circuits.
[11] Hyunseok Lee,et al. 7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[12] Mahmut T. Kandemir,et al. Amber*: Enabling Precise Full-System Simulation with Detailed Modeling of All SSD Resources , 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[13] Wook-Ghee Hahn,et al. 7.2 A 128Gb 3b/cell V-NAND flash memory with 1Gb/s I/O rate , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.
[14] Mahmut T. Kandemir,et al. SOML Read: Rethinking the Read Operation Granularity of 3D NAND SSDs , 2019, ASPLOS.
[15] Jun Li,et al. Pattern-based Write Scheduling and Read Balance-oriented Wear-Leveling for Solid State Drivers , 2019, 2019 35th Symposium on Mass Storage Systems and Technologies (MSST).
[16] Kiran Kumar Matam,et al. GraphSSD: Graph Semantics Aware SSD , 2019, 2019 ACM/IEEE 46th Annual International Symposium on Computer Architecture (ISCA).
[17] Fei Wu,et al. Characterizing 3D Floating Gate NAND Flash , 2018, SIGMETRICS.
[18] Tei-Wei Kuo,et al. A disturb-alleviation scheme for 3D flash memory , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
[19] Hamid Sarbazi-Azad,et al. Performance Evaluation of Dynamic Page Allocation Strategies in SSDs , 2016, ACM Trans. Model. Perform. Evaluation Comput. Syst..
[20] Youngjae Kim,et al. DFTL: a flash translation layer employing demand-based selective caching of page-level address mappings , 2009, ASPLOS.
[21] Hiroshi Nakamura,et al. 13.5 A 512Gb 3-bit/Cell 3D Flash Memory on 128-Wordline-Layer with 132MB/s Write Performance Featuring Circuit-Under-Array Technology , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).
[22] Mahmut T. Kandemir,et al. Invalid Data-Aware Coding to Enhance the Read Performance of High-Density Flash Memories , 2018, 2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[23] John Shalf,et al. OpenNVM: An open-sourced FPGA-based NVM controller for low level memory characterization , 2015, 2015 33rd IEEE International Conference on Computer Design (ICCD).
[24] Kyungmin Kim,et al. A 1Tb 4b/cell 64-stacked-WL 3D NAND flash memory with 12MB/s program throughput , 2018, 2018 IEEE International Solid - State Circuits Conference - (ISSCC).
[25] Hong Jiang,et al. Performance impact and interplay of SSD parallelism through advanced commands, allocation strategy and data granularity , 2011, ICS '11.
[26] Tei-Wei Kuo,et al. PWL: A progressive wear leveling to minimize data migration overheads for NAND flash devices , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[27] Mahmut T. Kandemir,et al. HIOS: A host interface I/O scheduler for Solid State Disks , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).
[28] Mohammad Arjomand,et al. Unleashing the potentials of dynamism for page allocation strategies in SSDs , 2014, SIGMETRICS '14.
[29] Onur Mutlu,et al. Improving 3D NAND Flash Memory Lifetime by Tolerating Early Retention Loss and Process Variation , 2018, SIGMETRICS.
[30] Heeseung Jo,et al. Superblock FTL: A superblock-based flash translation layer with a hybrid address translation scheme , 2010, TECS.
[31] David Hung-Chang Du,et al. Rejuvenator: A static wear leveling algorithm for NAND flash memory with minimized overhead , 2011, 2011 IEEE 27th Symposium on Mass Storage Systems and Technologies (MSST).
[32] Manabu Sato,et al. A 1.33-Tb 4-Bit/Cell 3-D Flash Memory on a 96-Word-Line-Layer Technology , 2020, IEEE Journal of Solid-State Circuits.
[33] Tei-Wei Kuo,et al. Improving Flash Wear-Leveling by Proactively Moving Static Data , 2010, IEEE Transactions on Computers.
[34] Jeong-Don Ihm,et al. 7.1 256Gb 3b/cell V-NAND flash memory with 48 stacked WL layers , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).
[35] Kyungmin Kim,et al. 13.4 A 512Gb 3-bit/Cell 3D 6th-Generation V-NAND Flash Memory with 82MB/s Write Throughput and 1.2Gb/s Interface , 2019, 2019 IEEE International Solid- State Circuits Conference - (ISSCC).
[36] Onur Mutlu,et al. Program interference in MLC NAND flash memory: Characterization, modeling, and mitigation , 2013, ICCD.
[37] Onur Mutlu,et al. Vulnerabilities in MLC NAND Flash Memory Programming: Experimental Analysis, Exploits, and Mitigation Techniques , 2017, 2017 IEEE International Symposium on High Performance Computer Architecture (HPCA).
[38] Mahmut T. Kandemir,et al. Sprinkler: Maximizing resource utilization in many-chip solid state disks , 2014, 2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA).
[39] Jonghoon Park,et al. 11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory , 2017, 2017 IEEE International Solid-State Circuits Conference (ISSCC).
[40] John Shalf,et al. TraceTracker: Hardware/software co-evaluation for large-scale I/O workload reconstruction , 2017, 2017 IEEE International Symposium on Workload Characterization (IISWC).