A Comparison Between Noise-Immunity Design Techniques for Dynamic Logic Gates

In this work, we analyze three design techniques to enhance the noise immunity of dynamic logic gates. A comparison in Power Consumption, Average Noise Threshold Energy (ANTE) and ANTE- normalized energy (EANTE) between the three techniques is presented. The dynamic logic gates using noise immunity techniques were designed with 0.35 mum, 0.18 mum, and 0.09 mum CMOS process technologies and power supply of 3.3 V, 1.8 V, and 1.0 V respectively. The obtained results show that for all technologies used in the simulations the Transparency Window technique [1] presents the best trade-off among noise immunity and performance as technology scales.

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