Synchronous latency insensitive design

It has long been recognized that the on-going scaling leads to severe problems with wire delays, which eventually will become a showstopper for further scaling. Several methods to mitigate these problems have been suggested, maybe the most realistic one being the global asynchronous local synchronous (GALS) approach. In the same time we have learned how to manage system complexity through powerful methodologies, design flows and tools, based on the very successful paradigm of synchronous logic. The problem we face now is how to combine this successful paradigm with the need for mitigating wire delays. In this paper we will give a brief overview of onchip interconnect properties and the wire delay crisis. We will shortly review various proposals to manage the wire delay problem. Finally we propose a new solution, synchronous latency insensitive design, which manages the wire delay problem without disturbing the synchronous paradigm. The new solution is a variation of the GALS approach, which accepts large variations in clock skew and data latency, is completely synchronous at RTL level, has a completely synchronous implementation and can be implemented with only standard digital library cells. The proposed approach can also be extended to multiple clock frequencies. Summary form given only.

[1]  Christer Svensson,et al.  Self-tested self-synchronization circuit for mesochronous clocking , 2001 .

[2]  Alberto L. Sangiovanni-Vincentelli,et al.  A methodology for correct-by-construction latency insensitive design , 1999, 1999 IEEE/ACM International Conference on Computer-Aided Design. Digest of Technical Papers (Cat. No.99CH37051).

[3]  Christer Svensson,et al.  Timing closure through a globally synchronous, timing partitioned design methodology , 2004, Proceedings. 41st Design Automation Conference, 2004..

[4]  Kurt Keutzer,et al.  Getting to the bottom of deep submicron , 1998, ICCAD '98.

[5]  Mark R. Greenstreet,et al.  A minimal source-synchronous interface , 2002, 15th Annual IEEE International ASIC/SOC Conference.

[6]  Christer Svensson Electrical interconnects revitalized , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[7]  Christer Svensson,et al.  Performance of Synchronous and Asynchronous Schemes for VLSI Systems , 1992, IEEE Trans. Computers.

[8]  F. Anceau A synchronous approach for clocking VLSI systems , 1982, IEEE Journal of Solid-State Circuits.

[9]  Jiang Xu,et al.  A wave-pipelined on-chip interconnect structure for networks-on-chips , 2003, 11th Symposium on High Performance Interconnects, 2003. Proceedings..

[10]  Mark R. Greenstreet,et al.  Efficient self-timed interfaces for crossing clock domains , 2003, Ninth International Symposium on Asynchronous Circuits and Systems, 2003. Proceedings..