Reducing instruction cache energy consumption using a compiler-based strategy
暂无分享,去创建一个
Wei Zhang | Mahmut T. Kandemir | Narayanan Vijaykrishnan | Mary Jane Irwin | Vijay Degalahal | Jie S. Hu
[1] Wei Zhang,et al. Compiler-directed instruction cache leakage optimization , 2002, MICRO.
[2] Scott Mahlke,et al. Three Superblock Scheduling Models for Superscalar and Superpipelined Processors , 1991 .
[3] Monica S. Lam,et al. The cache performance and optimizations of blocked algorithms , 1991, ASPLOS IV.
[4] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[5] Steven S. Muchnick,et al. Advanced Compiler Design and Implementation , 1997 .
[6] R. Hokinson,et al. Historical trend in alpha-particle induced soft error rates of the Alpha/sup TM/ microprocessor , 2001, 2001 IEEE International Reliability Physics Symposium Proceedings. 39th Annual (Cat. No.00CH37167).
[7] Tadahiro Kuroda,et al. Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design , 1996, J. VLSI Signal Process..
[8] Margaret Martonosi,et al. Cache decay: exploiting generational behavior to reduce cache leakage power , 2001, ISCA 2001.
[9] Kaushik Roy,et al. Reducing leakage in a high-performance deep-submicron instruction cache , 2001, IEEE Trans. Very Large Scale Integr. Syst..
[10] David Blaauw,et al. Drowsy caches: simple techniques for reducing leakage power , 2002, ISCA.
[11] David Blaauw,et al. Drowsy instruction caches: leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, MICRO.
[12] Mahmut T. Kandemir,et al. Leakage energy management in cache hierarchies , 2002, Proceedings.International Conference on Parallel Architectures and Compilation Techniques.
[13] B. Doyle. Poly Poly nitride Poly Poly Silicon Silicon Resist Silicon Silicon Silicon nitride Resist OxideOxide Oxide Oxide Silicon poly poly Oxide Oxide , 2002 .
[14] P. Hazucha,et al. Impact of CMOS technology scaling on the atmospheric neutron soft error rate , 2000 .
[15] Philip H. Sweany,et al. Improving software pipelining with unroll-and-jam , 1996, Proceedings of HICSS-29: 29th Hawaii International Conference on System Sciences.
[16] T. Sakurai,et al. A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current , 2000, IEEE Journal of Solid-State Circuits.
[17] Farid N. Najm,et al. Design techniques for gate-leakage reduction in CMOS circuits , 2003, Fourth International Symposium on Quality Electronic Design, 2003. Proceedings..
[18] Lorenzo Alvisi,et al. Modeling the effect of technology trends on the soft error rate of combinational logic , 2002, Proceedings International Conference on Dependable Systems and Networks.
[19] Changhong Dai,et al. Impact of CMOS process scaling and SOI on the soft error rates of logic processes , 2001, 2001 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.01 CH37184).
[20] Krste Asanovic,et al. Dynamic fine-grain leakage reduction using leakage-biased bitlines , 2002, ISCA.
[21] Richard B. Brown,et al. Ultra low-leakage power strategies for sub-1 V VLSI: novel circuit styles and design methodologies for partially depleted silicon-on-insulator (PD-SOI) CMOS technology , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..
[22] David Blaauw,et al. Analysis and minimization techniques for total leakage considering gate oxide leakage , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).
[23] Eric Rotenberg,et al. Adaptive mode control: A static-power-efficient cache design , 2003, TECS.
[24] Gurindar S. Sohi,et al. A static power model for architects , 2000, MICRO 33.
[25] Michael Wolfe,et al. High performance compilers for parallel computing , 1995 .
[26] Trevor Mudge,et al. Drowsy instruction caches. Leakage power reduction using dynamic voltage scaling and cache sub-bank prediction , 2002, 35th Annual IEEE/ACM International Symposium on Microarchitecture, 2002. (MICRO-35). Proceedings..
[27] Wei Zhang,et al. Exploiting VLIW schedule slacks for dynamic and leakage energy reduction , 2001, MICRO.
[28] Hiroyuki Tomiyama,et al. Data memory design considering effective bitwidth for low-energy embedded systems , 2002, 15th International Symposium on System Synthesis, 2002..
[29] Margaret Martonosi,et al. Managing leakage for transient data: decay and quasi-static 4T memory cells , 2002, ISLPED '02.