Statistical Dynamic Power Estimation Techniques
暂无分享,去创建一个
[1] Ibrahim N. Hajj,et al. Probabilistic simulation for reliability analysis of CMOS VLSI circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[2] Sachin S. Sapatnekar,et al. Power estimation considering statistical IC parametric variations , 1997, Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97.
[3] Vishwani D. Agrawal,et al. Enhanced dual-transition probabilistic power estimation with selective supergate analysis , 2005, 2005 International Conference on Computer Design.
[4] Jarrod A. Roy,et al. Min-cut floorplacement , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[5] Zuochang Ye,et al. An efficient algorithm for modeling spatially-correlated process variation in statistical full-chip leakage analysis , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.
[6] Sachin S. Sapatnekar,et al. Full-chip analysis of leakage power under process variations, including spatial correlations , 2005, Proceedings. 42nd Design Automation Conference, 2005..
[7] Jinjun Xiong,et al. Robust Extraction of Spatial Correlation , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] Chi-Ying Tsui,et al. Gate-level power estimation using tagged probabilistic simulation , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[9] Ping Yang,et al. A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..
[10] Farid N. Najm,et al. Transition density: a new measure of activity in digital circuits , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Vishwani D. Agrawal,et al. Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations , 2009, 2009 IEEE Computer Society Annual Symposium on VLSI.
[12] Farid N. Najm,et al. Modeling and Estimation of Full-Chip Leakage Current Considering Within-Die Correlation , 2007, 2007 44th ACM/IEEE Design Automation Conference.
[13] Martin D. F. Wong,et al. Dynamic power estimation for deep submicron circuits with process variation , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).
[14] Massoud Pedram,et al. Efficient estimation of dynamic power consumption under a real delay model , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[15] Navakanta Bhat,et al. Process Variability-Aware Statistical Hybrid Modeling of Dynamic Power Dissipation in 65 nm CMOS Designs , 2007, 2007 International Conference on Computing: Theory and Applications (ICCTA'07).
[16] Yici Cai,et al. Statistical modeling and analysis of chip-level leakage power by spectral stochastic method , 2009, ASP-DAC 2009.
[17] Kaushik Roy,et al. Power Estimation Under Uncertain Delays , 1998, Integr. Comput. Aided Eng..
[18] Kurt Keutzer,et al. Estimation of average switching activity in combinational and sequential circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[19] Sheldon X.-D. Tan,et al. Statistical full-chip dynamic power estimation considering spatial correlations , 2011, 2011 12th International Symposium on Quality Electronic Design.