Modeling SystemVerilog Assertions using SysML and CCSL

SystemVerilog is a popular hardware description and verification language (HDVL) aimed at designing and verifying present-day complex embedded systems. With the increasing number of design verification assertions, engineers always feel it difficult to manage the gap between the system specification and the design validation efforts and to cope with the time-to-market factors. We describe an approach for the modeling of system design as well as validation features using the UML standards like SysML, MARTE and CCSL. We demonstrate our approach using an example of traffic light controller.