On-chip Thermal Modeling Based on SPICE Simulation

With technology scaled to deep submicron regime, temperature and temperature gradient have emerged as important design criteria. Elevated temperatures, spatial and temporal temperature variations and on-chip hotspot not only affect timing in both transistors and interconnects but also degrade circuit reliability. A SPICE simulation based thermal modeling method is proposed in this paper. Experiments on a set of tests show the correlations between functional and spatial hotspots in a circuit implemented in STM 65nm technologies.

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