论文信息 - A low-voltage CMOS multiplier for RF applications (poster session)

A low-voltage CMOS multiplier for RF applications (poster session)

A low-voltage analog multiplier operating at 1.2V is presented. The multiplier core consists of four MOS transistors operating in the saturation region. The circuit exploits the quadratic relation between current and voltage of the MOS transistor in saturation. The circuit wasdesigned using standard 0.6μm CMOS technology. Simulation results indicate an IP3 of 4.9dBm and a spur free dynamic range of 45dB.

Franco Maloberti | Carl J. Debono | Joseph Micallef

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