On Clustering Without Replication in Combinatorial Circuits

In this paper, we consider the problem of clustering combinatorial circuits for delay minimization, when logic replication is not allowed CN. The problem of delay minimization when logic replication is allowed CA has been well studied, and is known to be solvable in polynomial-time [8]. However, unbounded logic replication can be quite expensive. Thus, CN is an important problem. We show that selected variants of CN are NP-hard. We also obtain approximability and inapproximability results for these problems.

[1]  Shantanu Dutt,et al.  VLSI circuit partitioning by cluster-removal using iterative improvement techniques , 1996, ICCAD 1996.

[2]  Erich Barke,et al.  Hierarchical partitioning , 1996, Proceedings of International Conference on Computer Aided Design.

[3]  Martin D. F. Wong,et al.  Minimum replication min-cut partitioning , 1996, Proceedings of International Conference on Computer Aided Design.

[4]  Abbas El Gamal,et al.  Min-cut replication in partitioned networks , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  Jason Cong,et al.  FlowMap: an optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[6]  I. Hameem Shanavas,et al.  Wirelength Minimization in Partitioning and Floorplanning Using Evolutionary Algorithms , 2011, VLSI Design.

[7]  Chung-Kuan Cheng,et al.  A replication cut for two-way partitioning , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Rajmohan Rajaraman,et al.  Optimal Clustering for Delay Minimization , 1993, 30th ACM/IEEE Design Automation Conference.

[9]  Dimitrios Kagaris.  On minimum delay clustering without replication , 2003, Integr..

[10]  M. Shih,et al.  Circuit partitioning under capacity and I/O constraints , 1994, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94.

[11]  Eugene L. Lawler,et al.  Module Clustering to Minimize Delay in Digital Networks , 1969, IEEE Transactions on Computers.

[12]  Thomas Koshy.  Boolean Algebra and Combinatorial Circuits , 2004 .

[13]  I. Hameem Shanavas,et al.  Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm , 2014 .

[14]  Robert K. Brayton,et al.  On clustering for minimum delay/ara , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.