Scalable GM / I Based MOSFET Model

Swiss Federal Institute of Technology (EPFL), Electronics Laboratories, Lausanne, Switzerland1. IntroductionThe continuing decrease of supply voltage toreduce power consumption of digital circuitsstrongly affects the design of the analog part ofmixed analog/digital ICs. As a consequence, MOStransistors in analog circuits often operate in moder-ate inversion. Compact MOSFET models for deepsub-micron technologies therefore need to describethe full operating range from weak to strong inver-sion in a physical and continuous way. Scalabilityover the full range of available geometries isrequired without resorting to a large number ofparameters or parameter “binning”.This paper describes a scalable and unified MOStransistor model based on the normalized transcon-ductance-to-current characteristic, ,used in the ‘EKV’ model [1][2]. This approachdescribes the transistor behavior at different currentlevels from weak to moderate and strong inversion.The new features with respect to previous model ver-sions are addressed here, in particular, a new univer-sal mobility degradation model due to vertical field,reverse short-channel effect (RSCE), drain-inducedbarrier lowering (DIBL), and bias-dependent seriesresistance. The large-signal static model as well asthe dynamic charges and thermal noise models arederived in a unified way and are valid in all modes ofoperation. The compact scalable model is a strongcandidate for application to deep sub-micron tech-nologies. It is efficient for parameter extraction andcircuit simulation and, due to its continuity, allevi-ates convergence problems. A single set of as few as25 process-related, intrinsic and extrinsic DC modelparameters can be extracted for all geometriesincluding short and narrow devices in a simple andstraightforward sequence.The drain current is derived under typicalassumptions for charge-sheet models and includesdrift and diffusion components [3] as well as majorphysical effects in a single equation:(1)where is the surface mobility including verticalfield dependence, is the gate oxide capaci-tance, is the thermal voltage, is the specificcurrent related to aspect ratio, and are sym-metrical forward and reverse normalized currents[1], depending on and , respec-tively, and is the slope factor depending on .The concept of the pinch-off voltage [1], whichis essentially a function of the gate voltage, is used toaccount for effects of doping concentration, such asthreshold voltage, body effect, charge-sharing forshort- and narrow-channel effects, RSCE, DIBL andnon-uniform doping [4][5]. represents the chan-nel voltage at a given gate voltage for which theinversion charge density in the channel becomesnegligible with respect to the depletion charge den-sity . accounts for channel length modula-tion (CLM). Velocity saturation is handled similarlyto [6]. The model is formulated symmetrically interms of and and has a hierarchical struc-ture. It also includes temperature effects and sub-strate current [7].2. Long-Channel ModelA means of integration for the drain current isprovided by the normalized conductance [1] where . Asuitable function is needed to describe the behaviorof [1][8], with correct asymptotes, which are 1in weak inversion and in strong inversion,respectively. A simple and accurate analyticalexpression has recently been proposed [9]:(2)Both (2) and the characteristic, cal-culated from the numerical solution of Poisson andGauss equations under uniform doping and long-channel assumptions, are plotted in Fig. 1a , withrespect to the normalized current in sat-uration, and are found to match very well. The abovenumerical characteristic varies negligibly over alarge range of doping levels and oxide thicknesses.The measured results from long-channel devices ofthree CMOS technologies, with minimum featuresizes ranging from 1 to 0.5 , are shown inFig. 1b to match (2) very well from weak to stronginversion. For scaled deep sub-micron technologies,this characteristic is expected to remain sufficientlyg