A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput (40∼100 Mbps), the hardware cost is still affordable for 3GPP’s (3rd generation partnership project) interleaver.

[1]  Assefaw H. Gebremedhin,et al.  Scalable parallel graph coloring algorithms , 2000 .

[2]  Ran Ginosar,et al.  Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders , 2005, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[3]  Sergio Benedetto,et al.  Mapping interleaving laws to parallel turbo and LDPC decoder architectures , 2004, IEEE Transactions on Information Theory.

[4]  Paul Guinand,et al.  High-performance low-memory interleaver banks for turbo-codes , 2001, IEEE 54th Vehicular Technology Conference. VTC Fall 2001. Proceedings (Cat. No.01CH37211).

[5]  Norbert Wehn,et al.  Optimized concurrent interleaving architecture for high-throughput turbo-decoding , 2002, 9th International Conference on Electronics, Circuits and Systems.

[6]  Brian K. Classon,et al.  Contention-free interleavers , 2004, International Symposium onInformation Theory, 2004. ISIT 2004. Proceedings..

[7]  S. Benedetto,et al.  Variable-size interleaver design for parallel turbo decoder architectures , 2005, IEEE Transactions on Communications.

[8]  Kwyro Lee,et al.  Design of dividable interleaver for parallel decoding in turbo codes , 2002 .

[9]  Sergio Benedetto,et al.  Mapping interleaving laws to parallel turbo decoder architectures , 2004, IEEE Communications Letters.