The IEEE Boundary Scan Standard: A Test Paradigm to Ensure Hardware System Quality
暂无分享,去创建一个
[1] Bernard Courtois,et al. CAD and testing of ICs and systems: where are we going? , 1994 .
[2] Clay S. Gloster,et al. Boundary scan with cellular-based built-in self-test , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[3] Najmi T. Jarwala,et al. A unified theory for designing optimal test generation and diagnosis algorithms for board interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[4] Edward McCluskey,et al. Built-In Self-Test Techniques , 1985, IEEE Design & Test of Computers.
[5] Prabhakar Goel,et al. Electronic Chip-In-Place Test , 1982, DAC 1982.
[6] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[7] Prawat Nagvajara,et al. Pseudorandom testing for boundary-scan design with built-in self-test , 1991, IEEE Design & Test of Computers.
[8] Rodham E. Tulloss,et al. The Test Access Port and Boundary Scan Architecture , 1990 .
[9] William H. Kautz,et al. Testing for Faults in Wiring Networks , 1974, IEEE Transactions on Computers.
[10] Frans P. M. Beenker. Systematic and Structured Methods for Digital Board Testing , 1985, ITC.
[11] Peter Hansen,et al. Testing conventional logic and memory clusters using boundary scan devices as virtual ATE channels , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[12] Najmi T. Jarwala,et al. A new framework for analyzing test generation and diagnosis algorithms for wiring interconnects , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.
[13] Johnny J. LeBlanc,et al. LOCST: A Built-In Self-Test Technique , 1984, IEEE Design & Test of Computers.
[14] M. P. J. Stevens,et al. System-level testability of hardware/software systems , 1994, Proceedings., International Test Conference.
[15] Vinod K. Agarwal,et al. Testing and diagnosis of interconnects using boundary scan architecture , 1988, International Test Conference 1988 Proceeding@m_New Frontiers in Testing.
[16] Marcelo Lubaszewski,et al. A pragmatic test and diagnosis methodology for partially testable MCMs , 1994, Proceedings of IEEE Multi-Chip Module Conference (MCMC-94).
[17] Marcelo Lubaszewski,et al. Unifying test and diagnosis of interconnects and logic clusters in partial boundary scan boards , 1993, Proceedings of 1993 International Conference on Computer Aided Design (ICCAD).
[18] R. E. Tulloss,et al. BIST and boundary-scan for board level test: test program pseudocode , 1989, [1989] Proceedings of the 1st European Test Conference.
[19] Paul Wagner,et al. INTERCONNECT TESTING WITH BOUNDARY SCAN , 1987 .
[20] Marcelo Lubaszewski,et al. On the design of self-checking boundary scannable boards , 1992, Proceedings International Test Conference 1992.
[21] Kenneth P. Parker,et al. The Boundary-Scan Handbook , 1992, Springer US.
[22] Ben Bennetts,et al. IEEE standard 1149.1-1990 on boundary scan: History, literature survey, and current status , 1991, J. Electron. Test..
[23] Thomas W. Williams,et al. Design for Testability - A Survey , 1982, IEEE Trans. Computers.