ASIC implementation of high speed processor for computing fast hartley transformation

The improvement in speed and power for the computation of Discrete Hartley Transformation (DHT) using parallel addition technique is well established, but all the work have been reported in gate (FPGA) level. In this paper transistor level (ASIC) implementation technique for computation of high speed processor of prime length one dimensional Fast Hartley Transformation (FHT) based on MAC is reported for the first time. Equation formulation methodology for the transformation of such processors offered a technique of parallelism, also ensure substantial reduction of pre and post processing stages, owing towards high speed operation. The functionality of these circuits was checked and performance parameters like propagation delay, dynamic power consumptions were calculated through spice spectre using 45nm CMOS technology. The implementation methodology ensure substantial reduction of propagation delay in comparison with CORDIC, parallel adder (PA), distributed arithmetic and circular convolution (CC) based implementation which is most commonly used architecture, reported so far, for DHT processors. The propagation delay of the resulting 16 point FHT processor is only ~7.68μs while the power consumption of the same was ~90.5mW only. Almost 50% improvement in speed from earlier reported FHT processors, e.g. CORDIC, PA and CC based implementation methodology, has been achieved.