Robust FPGA Design under Variations

This paper briefly describes the PhD research work on Robust FPGA Design Under Variations. The work proposes design techniques in three primary areas, viz., power yield enhancement, timing yield enhancement and IR-drop reduction. An architecture and CAD enhancement technique is proposed for improving the timing yield of FPGAs under process variations. Two different techniques are proposed for improving the power yield of FPGAs under process variations. The first technique reduces spatial correlation among leaking blocks to reduce leakage variability, whereas the second technique sizes the transistors of the buffers in the interconnects to reduce leakage variability. For IR-drop reduction, two different CAD techniques are proposed. The first design methodology is an IR-drop aware place and route technique which reduces local switching activities in a region to reduce IR-drops. The second approach is an IR-drop aware clustering methodology. This methodology reduces the clustering of high switching activity nets in a logic cluster to improve the supply voltage profile.