Design and FPGA implementation of iterative decoders for codes on graphs

This work presents a Field Programmable Gate Array (FPGA) implementation of the Min-Sum iterative decoding algorithm for the (8,4) extended Hamming code using a reconfigurable computing system. The Mitrion-C high level language (HLL) is used to program the FPGAs, since it provides flexible tools for FPGA-based prototyping and functional verification for hardware design. A hardware-efficient implementation of the Min-step in the Min-Sum decoder, which eliminates the use of floating point multipliers, is also presented. The parallelism offered by the Min-Sum algorithm is exploited in hardware, resulting in a 15 fold speedup over optimized software implementations. The performance of the hardware implementation is virtually the same as that predicted by computer simulations, validating the hardware design.

[1]  Jinghu Chen,et al.  Density evolution for two improved BP-Based decoding algorithms of LDPC codes , 2002, IEEE Communications Letters.

[2]  J. J. Koo,et al.  Modelling and Implementation of a Novel SPR Biointerface for Time-Effective Detection of Sepsis Biomarkers , 2007 .

[3]  Alberto Morello,et al.  DVB-S2: The Second Generation Standard for Satellite Broad-Band Services , 2006, Proceedings of the IEEE.

[4]  Brendan J. Frey,et al.  Factor graphs and the sum-product algorithm , 2001, IEEE Trans. Inf. Theory.

[5]  Christian Schlegel,et al.  Trellis and turbo coding , 2004 .

[6]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[7]  Marc P. C. Fossorier,et al.  Two-dimensional correction for min-sum decoding of irregular LDPC codes , 2006, IEEE Communications Letters.

[8]  Rüdiger L. Urbanke,et al.  The renaissance of Gallager's low-density parity-check codes , 2003, IEEE Commun. Mag..

[9]  Rüdiger L. Urbanke,et al.  Design of capacity-approaching irregular low-density parity-check codes , 2001, IEEE Trans. Inf. Theory.

[10]  B. Achiriloaie,et al.  VI REFERENCES , 1961 .

[11]  J.E. Mazo,et al.  Digital communications , 1985, Proceedings of the IEEE.

[12]  David Fernández,et al.  Evaluation of a High-Level-Language Methodology for High-Performance Reconfigurable Computers , 2007, 2007 IEEE International Conf. on Application-specific Systems, Architectures and Processors (ASAP).

[13]  Ezio Biglieri,et al.  Coding for Wireless Channels , 2005 .

[14]  David J. C. MacKay,et al.  Good Error-Correcting Codes Based on Very Sparse Matrices , 1997, IEEE Trans. Inf. Theory.

[15]  Hideki Imai,et al.  Reduced complexity iterative decoding of low-density parity check codes based on belief propagation , 1999, IEEE Trans. Commun..

[16]  Robert Michael Tanner,et al.  A recursive approach to low complexity codes , 1981, IEEE Trans. Inf. Theory.