Reversible logic implementation of AES algorithm

Since the selection of the Rijndael cryptosystem as a new Advanced Encryption Standard (AES) in 2000, many hardware implementations of AES have been reported. Some of these implementations are optimized for speed, some for area, some for reconfigurability, and some for low-power applications. Again, reversible logic synthesis methodologies have drawn the attention of researchers in recent times, mainly with the prospect of quantum computing becoming a reality, and the potential of reversible logic circuits for providing ultra low-power implementations. Although many of the cryptographic primitives are inherently reversible by nature, very little work has been done towards reversible logic implementations of the same. The only published works relate to reversible implementations of Montgomery multiplication algorithm, which has applications in cryptography. The present paper, possibly for the first time, presents a reversible logic implementation of a block cipher, namely, 128-bit AES. The various AES functional blocks have been synthesized using reversible gates, using which an overall reversible architecture has been proposed. The pipelined version as suggested can only be used in the Electronic Code Book (ECB) mode. The hardware complexity of the implementation has been evaluated using the number of reversible gates required and the quantum cost.

[1]  Francisco Rodríguez-Henríquez,et al.  Cryptographic Algorithms on Reconfigurable Hardware , 2010 .

[2]  Robert Wille,et al.  Improving ESOP-Based Synthesis of Reversible Logic Using Evolutionary Algorithms , 2011, EvoApplications.

[3]  Guowu Yang,et al.  Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[4]  Hafiz Md. Hasan Babu,et al.  Efficient Reversible Montgomery Multiplier and Its Application to Hardware Cryptography , 2009 .

[5]  M. Thornton,et al.  ESOP-based Toffoli Gate Cascade Generation , 2007, 2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing.

[6]  J. E. Rice,et al.  A Shared-cube Approach to ESOP-based Synthesis of Reversible Logic , 2011 .

[7]  Barenco,et al.  Elementary gates for quantum computation. , 1995, Physical review. A, Atomic, molecular, and optical physics.

[8]  Gerhard W. Dueck,et al.  A transformation based algorithm for reversible logic synthesis , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[9]  Charles H. Bennett,et al.  Logical reversibility of computation , 1973 .

[10]  Siva Sai Yerubandi,et al.  Differential Power Analysis , 2002 .

[11]  Mark Zwolinski,et al.  Reversible Logic to Cryptographic Hardware: A New Paradigm , 2006, 2006 49th IEEE International Midwest Symposium on Circuits and Systems.

[12]  A. Mishchenko,et al.  Fast Heuristic Minimization of Exclusive-Sums-of-Products , 2001 .

[13]  R. Landauer,et al.  Irreversibility and heat generation in the computing process , 1961, IBM J. Res. Dev..

[14]  Robert Wille,et al.  BDD-based synthesis of reversible logic for large functions , 2009, 2009 46th ACM/IEEE Design Automation Conference.

[15]  Robert Wille,et al.  Exact Multiple-Control Toffoli Network Synthesis With SAT Techniques , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.