CMOS high-frequency switched-capacitor filters for telecommunication applications

A digitally programmable high-frequency switched-capacitor filter for use in a switched digital video (SDV/VDSL) link is described. The highest available clock frequency in the system is 51.84 MHz (f/sub s/=2f/sub clock/=103.68 MHz for double sampling) while the three desired low-pass corner frequencies (f/sub c/) are 8,12, and 20 MHz. The double-sampling, bilinear, elliptic, fifth-order switched-capacitor filter meets the desired -40-dB attenuation at 1.3 f/sub c/, and -30 dB at 1.25 f/sub c/. For the 12-MHz corner frequency setting, given the 2V/sub pp/ differential input, the measured worst case total harmonic distortion is -60 dB, with signal-to-noise ratio of 54 dB. The analog power dissipation is 125 mW from a 5-V power supply. The test results indicate that the clock frequency can be increased to 73 MHz without any ill effects. More measurements verify that an all-digital CMOS implementation, utilizing metal-sandwich capacitors, performs as well as the special-layer analog capacitors implementation, with a small reduction in the absolute corner frequencies. The prototype IC's are fabricated in a 0.35-/spl mu/m 5-V (0.48 /spl mu/m drawn) CMOS process.

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