A new gate configuration, the latched domino (Ldomino) CMOS gate, is presented. It can be used to alleviate the inversion problem inherent in domino CMOS, while improving speed and reducing layout area. Ldomino logic can serve as an efficient interface stage between blocks of static and domino or differential-cascode voltage-switch logic. The function of interfacing single-ended logic signals to differential domino-compatible logic signals is combined with the capability of efficient implementation of complex logic functions, thereby improving the logic flexibility of domino logic. A simple 4-bit ALU is used as an illustrative example of the application of Ldomino logic.
[1]
L. Heller,et al.
Cascode voltage switch logic: A differential CMOS logic family
,
1984,
1984 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[2]
C.A.T. Salama,et al.
Analysis and design optimization of domino CMOS logic with application to standard cells
,
1985,
IEEE Journal of Solid-State Circuits.
[3]
C. M. Lee,et al.
High-speed compact circuits with CMOS
,
1982
.
[4]
N. F. Goncalves,et al.
NORA: a racefree dynamic CMOS technique for pipelined logic structures
,
1983
.
[5]
C.A.T. Salama,et al.
Latched domino CMOS logic
,
1985
.