High Aspect Ratio Vertical Through-Vias for 3D MEMS Packaging Applications by Optimized Three-Step Deep RIE
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[1] Junghoon Yeom,et al. Maximum achievable aspect ratio in deep reactive ion etching of silicon due to aspect ratio dependent transport and the microloading effect , 2005 .
[2] S. Spearing,et al. Effect of process parameters on the surface morphology and mechanical performance of silicon structures after deep reactive ion etching (DRIE) , 2002 .
[3] Jianmin Miao,et al. Study of surface treatment processes for improvement in the wettability of silicon-based materials used in high aspect ratio through-via copper electroplating , 2007 .
[4] D. L. Kendall. Vertical Etching of Silicon at very High Aspect Ratios , 1979 .
[5] F. Marty,et al. Advanced etching of silicon based on deep reactive ion etching for silicon high aspect ratio microstructures and three-dimensional micro- and nanostructures , 2005, Microelectron. J..
[6] Bo Tan,et al. Deep micro hole drilling in a silicon substrate using multi-bursts of nanosecond UV laser pulses , 2005 .
[7] Jianmin Miao,et al. Through-wafer electroplated copper interconnect with ultrafine grains and high density of nanotwins , 2007 .
[8] Miko Elwenspoek,et al. The black silicon method: a universal method for determining the parameter setting of a fluorine-based reactive ion etcher in deep silicon trench etching with profile control , 1995 .
[9] S. Jeanneret,et al. Advanced deep reactive ion etching: a versatile tool for microelectromechanical systems , 1998 .
[10] S. Moon,et al. Dependences of bottom and sidewall etch rates on bias voltage and source power during the etching of poly-Si and fluorocarbon polymer using SF6, C4F8, and O2 plasmas , 2004 .
[11] Jyrki Kiihamäki,et al. Etching through silicon wafer in inductively coupled plasma , 2000 .
[12] Ole Hansen,et al. Study of the Roughness in a Photoresist Masked, Isotropic, SF6-Based ICP Silicon Etch , 2006 .
[13] H. W. Lau,et al. High aspect ratio submicron silicon pillars fabricated by photoassisted electrochemical etching and oxidation , 1995 .
[14] Jyrki Kiihamäki. Deceleration of silicon etch rate at high aspect ratios , 2000 .
[15] Yong-Kweon Kim,et al. Prevention method of a notching caused by surface charging in silicon reactive ion etching , 2005 .
[16] Martin A. Schmidt,et al. Influence of Coil Power on the Etching Characteristics in a High Density Plasma Etcher , 1999 .
[17] Ivo W. Rangelow,et al. Critical tasks in high aspect ratio silicon dry etching for microelectromechanical systems , 2003 .
[18] J. Miao,et al. Aspect-Ratio-Dependent Copper Electrodeposition Technique for Very High Aspect-Ratio Through-Hole Plating , 2006 .
[19] Wensyang Hsu,et al. Sidewall roughness control in advanced silicon etch process , 2003 .
[20] M. Schmidt,et al. Characterization of a Time Multiplexed Inductively Coupled Plasma Etcher , 1999 .
[21] S. Aachboun,et al. Deep anisotropic etching of silicon , 1999 .
[22] J. Miao,et al. Effect of Clamping Ring Materials and Chuck Temperature on the Formation of Silicon Nanograss in Deep RIE , 2006 .
[23] Róbert Juhász,et al. Formation of three-dimensional microstructures by electrochemical etching of silicon , 2001 .
[24] Etching High Aspect Ratio Silicon Trenches , 2003 .
[25] Jianmin Miao,et al. Fabrication of high aspect ratio 35 μm pitch through-wafer copper interconnects by electroplating for 3-D wafer stacking , 2006 .
[26] E. V. D. Drift,et al. Balancing the etching and passivation in time-multiplexed deep dry etching of silicon , 2001 .
[27] W. Pike,et al. Analysis of sidewall quality in through-wafer deep reactive-ion etching , 2004 .