A method and a control unit for realizing the optimization of power storage adapters with interlinked hardware operations that minimize the interaction between hardware and firmware, as well as a circuit design structure on which the circuit of the relevant control unit is located. The control unit includes a plurality of hardware modules; and one or more processors. An event queue is associated with at least one processor, and notifies the processor via a plurality of predefined events. A control block is used to control an operation in one of the plurality of hardware modules, including writing an event queue entry owned by the hardware module. A plurality of control blocks is selectively placed in a pre-defined chain in order to minimize the writing event queue entries to the processor by the hardware module.