Estimation for equivalent thermal conductivity of silicon-through vias TSVs used for 3D IC integration

In this study, thermal performance of 3D IC integration is investigated. Emphasis is placed on the determination of a set of equivalent thermal conductivity equations for Cu-filled TSVs with various TSV diameters, TSV pitches, TSV thicknesses, passivation thicknesses, and microbump pads. Also, a slice model to imitate a 3D memory stacked chip is adopted to verify the accuracy of the equivalent equations. Finally, the feasibility of these equivalent equations is demonstrated through a simple 3D IC integration structure.

[1]  John H. Lau,et al.  TSV Interposers With Embedded Microchannels for 3D IC and LED Integration , 2011 .

[2]  John H. Lau,et al.  3D packaging with through ilicon via (TSV) for electrical and fluidic interconnections , 2009, 2009 59th Electronic Components and Technology Conference.

[3]  John H. Lau,et al.  Effects of TSV (Through Silicon Via) interposer/chip on the thermal performances of 3D IC packaging , 2009 .

[5]  A. Jain,et al.  Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits , 2010, IEEE Transactions on Components and Packaging Technologies.

[6]  D. Pinjala,et al.  Fabrication of Silicon Carriers With TSV Electrical Interconnections and Embedded Thermal Solutions for High Power 3-D Packages , 2009, IEEE Transactions on Components and Packaging Technologies.

[7]  D. Pinjala,et al.  3-D Packaging With Through-Silicon Via (TSV) for Electrical and Fluidic Interconnections , 2013, IEEE Transactions on Components, Packaging and Manufacturing Technology.

[8]  Siow Pin Tan,et al.  Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules , 2010, IEEE Transactions on Components and Packaging Technologies.

[9]  E. Beyne,et al.  Thermal test vehicle for the validation of thermal modelling of hot spot dissipation in 3D stacked ICs , 2010, 3rd Electronics System Integration Technology Conference ESTC.

[10]  John H. Lau,et al.  Thermal-Enhanced and Cost-Effective 3D IC Integration With TSV (Through-Silicon Via) Interposers for High-Performance Applications , 2010 .

[11]  Sheng-Tsai Wu,et al.  Thermo-mechanical simulative study for 3D vertical stacked IC packages with spacer structures , 2010, 2010 26th Annual IEEE Semiconductor Thermal Measurement and Management Symposium (SEMI-THERM).

[12]  E. Beyne,et al.  Steady state and transient thermal analysis of hot spots in 3D stacked ICs using dedicated test chips , 2011, 2011 27th Annual IEEE Semiconductor Thermal Measurement and Management Symposium.

[13]  Ankur Jain,et al.  Thermal characteristics of multi-die, three-dimensional integrated circuits with unequally sized die , 2010, 2010 12th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems.

[14]  N. Kernevez,et al.  Challenges for 3D IC integration: bonding quality and thermal management , 2007, 2007 IEEE International Interconnect Technology Conferencee.

[15]  William R. Eisenstadt,et al.  High speed I/O and thermal effect characterization of 3D stacked ICs , 2009, 2009 IEEE International Conference on 3D System Integration.

[16]  John H. Lau,et al.  Effect of TSV interposer on the thermal performance of FCBGA package , 2009, 2009 11th Electronics Packaging Technology Conference.

[17]  John H. Lau,et al.  A thermal performance measurement method for blind through silicon vias (TSVs) in a 300mm wafer , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).

[18]  J. Lau,et al.  Thermal management of 3D IC integration with TSV (through silicon via) , 2009, 2009 59th Electronic Components and Technology Conference.