Modeling and Detectability of Full Open Gate Defects in FinFET Technology

FinFET technology is an attractive candidate for high-performance and power-efficient application and is currently used for several electronic products. FinFET technology incorporates new technologies in the manufacturing processes that may generate new defect topologies which need to be considered during test generation. This paper analyzes the electrical behavior of full open gate defects, i.e., a transistor gate with infinite resistance. It is shown that classical models, called single open (SO) and interconnect open (IO), that have been proposed in the past for CMOS technology are not sufficient in FinFET technology. The modern FinFET-based logic cells using multifin and multifinger design techniques give rise to new specific defect topologies called “subset full open gate defect.” The static and dynamic electrical behaviors of the two new topologies, subset SO (SOsub) and subset IO (IOsub), are analyzed, and the detectability of the defect in the context of Boolean testing and delay testing is derived. The detectability is analyzed taking into account process variation, temperature, and power supply control.

[1]  Xiaolang Yan,et al.  Scratch-concerned yield modeling for IC manufacturing involved with a chemical mechanical polishing process , 2012, Journal of Zhejiang University SCIENCE C.

[2]  Antonio Rubio,et al.  Electrical model of the floating gate defect in CMOS ICs: implications on IDDQ testing , 1994, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[3]  Mark Y. Liu,et al.  A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 SRAM cell size , 2014, 2014 IEEE International Electron Devices Meeting.

[4]  Víctor H. Champac,et al.  Testing of Stuck-Open Faults in Nanometer Technologies , 2012, IEEE Design & Test of Computers.

[5]  A. N. Bhoj,et al.  Fault Models for Logic Circuits in the Multigate Era , 2012, IEEE Transactions on Nanotechnology.

[6]  M. Choe,et al.  Technology scaling on High-K & Metal-Gate FinFET BTI reliability , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[7]  Tiago R. Balen,et al.  Analyzing the behavior of FinFET SRAMs with resistive defects , 2017, 2017 IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC).

[8]  A. Thamm,et al.  Overview of dual damascene integration schemes in Cu BEOL integration , 2008 .

[9]  Qiang Xu,et al.  On modeling faults in FinFET logic circuits , 2012, 2012 IEEE International Test Conference.

[10]  A. J. Mouthaan,et al.  Mechanical stress evolution and the blech length: 2D simulation of early electromigration effects , 1998 .

[11]  David Z. Pan,et al.  Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line Conflict , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Jim Johnson,et al.  SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing , 2015, IEEE Transactions on Electron Devices.

[13]  P. Gupta,et al.  Device- and Circuit-Level Variability Caused by Line Edge Roughness for Sub-32-nm FinFET Technologies , 2012, IEEE Transactions on Electron Devices.

[14]  Jinjun Xiong,et al.  Robust Extraction of Spatial Correlation , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[15]  André Ivanov,et al.  Testing for floating gates defects in CMOS circuits , 1998, Proceedings Seventh Asian Test Symposium (ATS'98) (Cat. No.98TB100259).

[16]  Emanuele Baravelli,et al.  Fin shape fluctuations in FinFET: Correlation to electrical variability and impact on 6-T SRAM noise margins , 2009 .

[17]  Tsu-Jae King Liu,et al.  Gate Line Edge Roughness Model for Estimation of FinFET Performance Variability , 2009, IEEE Transactions on Electron Devices.

[18]  Chenming Hu,et al.  Modeling Advanced FET Technology in a Compact Model , 2006, IEEE Transactions on Electron Devices.

[19]  Keith Baker,et al.  Defect-based delay testing of resistive vias-contacts a critical evaluation , 1999, International Test Conference 1999. Proceedings (IEEE Cat. No.99CH37034).

[20]  Robert V. Brill,et al.  Applied Statistics and Probability for Engineers , 2004, Technometrics.

[21]  Amit Karel,et al.  Resistive Bridging Defect Detection in Bulk, FDSOI and FinFET Technologies , 2017, J. Electron. Test..

[22]  H. J. Kim,et al.  Considering physical mechanisms and geometry dependencies in 14nm FinFET circuit aging and product validations , 2015, 2015 IEEE International Electron Devices Meeting (IEDM).

[23]  Chris Ngai,et al.  Defect gallery and bump defect reduction in the self Aligned Double Patterning module , 2010, 2010 IEEE/SEMI Advanced Semiconductor Manufacturing Conference (ASMC).

[24]  Friedrich Hapke,et al.  Diagnosing timing related cell internal defects for FinFET technology , 2015, VLSI Design, Automation and Test(VLSI-DAT).

[25]  Ali M. Niknejad,et al.  Compact Modeling of Variation in FinFET SRAM Cells , 2010, IEEE Design & Test of Computers.

[26]  F. Joel Ferguson,et al.  An unexpected factor in testing for CMOS opens: the die surface , 1996, Proceedings of 14th VLSI Test Symposium.

[27]  Yu Shaofeng,et al.  Optimization of STI oxide recess uniformity for FinFET beyond 20nm , 2015, 2015 China Semiconductor Technology International Conference.

[28]  Michel Renovell,et al.  Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[29]  Kazuhiko Endo,et al.  Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation , 2010, IEEE Transactions on Electron Devices.

[30]  S. Demuynck,et al.  Reliability of MOL local interconnects , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[31]  C. Auth,et al.  A 10nm high performance and low-power CMOS technology featuring 3rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects , 2017, 2017 IEEE International Electron Devices Meeting (IEDM).