Power consumption of static and dynamic CMOS circuits: a comparative study

The choice of technology to be used for the implementation of a given specification is usually dependent on the optimization and the performance constraints that the finished chip is required to meet. When the target is low-power dissipation, one of the decisions that the designer has to take concerns the use of static versus dynamic CMOS transistors. Although, from the theoretical stand-point, the main advantages and disadvantages of both technologies are quite well established, no experiment-driven guidelines have been provided so far to VLSI designers regarding this specific aspect. In this paper, we present the results of an empirical investigation we have carried out on a large set of benchmarks, and we comment on the experimental evidence.